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參數(shù)資料
| 型號： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標(biāo)設(shè)備的32位 |
| 文件頁數(shù)： | 108/190頁 |
| 文件大小： | 748K |
| 代理商： | S5935 |
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8-100
ADD-ON BUS INTERFACE
S5935
The internal interfaces of the S5935 allow Add-On
Operation Registers to be accessed asynchronous to
BPCLK (synchronous to the rising edge of the read
or write strobe). The exception to this is the Add-On
General Control/Status Register. This is due to the
async nature of FIFO status bits changing as the PCI
bus reads data. For Pass-Thru operations, the Pass-
Thru Data Register accesses are synchronous to
BPCLK to support burst transfers. The FIFO port is
also accessed synchronous to BPCLK.
Asynchronous Register Accesses
For many Add-On applications, Add-On logic does not
operate at the PCI bus frequency. This is especially true
for Add-Ons implementing a microprocessor, which
may be operating at a lower (or higher) frequency. Fig-
ures 1 and 2 show asynchronous Add-On Operation
Register accesses. Exact AC timings are detailed in the
Electrical and AC Characteristics chapter (Chapter 13).
For asynchronous reads (Figure 1), data is driven on
the data bus when RD# is asserted. When RD# is not
asserted, the DQ[31:0] outputs float. A valid address
and valid byte enables must be presented before cor-
rect data is driven. RD# has both a minimum inactive
time and a minimum active time for asynchronous ac-
cesses.
For asynchronous writes (Figure 2), data is clocked
into the S5935 on the rising edge of the WR# input.
Address, byte enables, and data must all meet setup
and hold times relative to the rising edge or WR#.
WR# has both a minimum inactive time and a mini-
mum active time for asynchronous accesses
Synchronous FIFO and Pass-Thru
Data Register Accesses
To obtain the highest data transfer rates possible,
Add-On logic should operate synchronously with the
PCI clock. The buffered PCI clock (BPCLK) is pro-
vided for this purpose. A synchronous interface with
Pass-Thru mode or the FIFO allows data to be trans-
ferred at the maximum PCI bus bandwidth (132
MBytes/sec) by allowing burst accesses with the Add-
On interface. The RD# and WR# inputs become en-
ables, using BPCLK to clock data into and out of
registers. This section applies only to synchronous ac-
cesses to the FIFO (AFIFO) and Pass-Thru Data
(APTD) registers.
Figures 3 and 4 show single-cycle, synchronous
FIFO and Pass-Thru Operation Register accesses.
Exact AC timings are detailed in the Electrical and
AC Characteristics chapter.
For synchronous reads (Figure 3), data is driven onto
the data bus when RD# (or RDFIFO#) is asserted.
When RD# is not asserted, the DQ[31:0] outputs
float. The address, byte enable, and RD# inputs must
meet setup and hold times relative to the rising edge
of BPCLK. Burst reads may be performed by holding
RD# low.
For synchronous writes (Figure 4), data is clocked
into the register on the rising edge of BPCLK. Ad-
dress, byte enables, and data must all meet setup
and hold times relative to the rising edge or BPCLK.
Burst writes may be performed by holding WR# (or
WRFIFO#) low. When holding WR# low, data is
clocked in on each BPCLK rising edge.
nv Memory Accesses Through the Add-On
General Control/Status Register
To access nv memory contents through the Add-On
General Control/Status Register (AGCSTS), special
considerations must be made. Internally, all nv memory
accesses by the S5935 are synchronized to a divided-
down version of the PCI bus clock. Because of this, if
nv memory accesses are performed through the
AGCSTS register, the register access must be synchro-
nized to BPCLK. The rising edge RD# or WR# is still
used to clock data, but these inputs along with the ad-
dress and byte enables are synchronized to BPCLK.
Accesses to AGCSTS for monitoring FIFO or mailbox
status, etc., may be done asynchronous to BPCLK.
MAILBOX BUS INTERFACE
The mailbox register names may need some clarifi-
cation. For the Add-On interface, an outgoing mail-
box refers to a mailbox sending information to the
PCI bus. An incoming mailbox refers to a mailbox
receiving information from the PCI bus. An outgoing
mailbox on the Add-On interface is, internally, the
same as the corresponding incoming mailbox on the
PCI interface and vice-versa.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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