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參數(shù)資料
| 型號(hào)： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標(biāo)設(shè)備的32位 |
| 文件頁(yè)數(shù)： | 77/190頁(yè) |
| 文件大小： | 748K |
| 代理商： | S5935 |
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5-69
ADD-ON BUS OPERATION REGISTERS
S5935
Table 3. Interrupt Control/Status Register
31:24
Reserved. Always zero.
23
Interrupt asserted. This read-only status bit indicates that one or more interrupt conditions is
present. This bit is nothing more than the ORing of the interrupt conditions described by bits, 20,
17 and 16 of this register.
22
Reserved. Always zero.
21
Master/Target Abort. This bit signifies that an interrupt has been generated due to the S5935
encountering a Master or Target abort during an S5935 initiated PCI bus cycle. This bit operates
as read or write one clear. Writing a one to this bit causes it to be cleared. Writing a zero to this
bit does nothing.
20
BIST. Built-In Self-Test interrupt. This interrupt occurs when a self test is initiated by the PCI
interface writing of the BIST configuration register. This bit will stay set until cleared by writing a
one to this location. Self test completion codes may be passed to the PCI BIST register by writing
to the AGCSTS register.
19
Read Transfer Complete. This bit signifies that an interrupt has been generated due to the
completion of a PCI bus master operation involving the transfer of data from the PCI bus to the
Add-On. This interrupt will occur when the Master Read Transfer Count register reaches zero.
This bit operates as read or write one clear. A write to this bit with the data of one will cause this
bit to be reset; a write to this bit with the data of zero will not change the state of this bit.
18
Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completion
of a PCI bus master operation involving the transfer of data to the PCI bus from the Add-On. This
interrupt will occur when the Master Write Transfer Count register reaches zero. This bit operates as
read or write one clear. A write to this bit with the data of one will cause this bit to be reset; a write to
this bit with the data of zero will not change the state of this bit.
17
Outgoing Mailbox Interrupt. This bit sets when the mailbox selected by bits 12 through 8 of this
register is read by the PCI interface. This bit operates as read or write one clear. A write to this bit
with the data as one will cause this bit to be reset; a write to this bit with the data as zero will not
change the state of this bit.
16
Incoming Mailbox Interrupt. This bit sets when the mailbox selected by bits 4 through 0 of this
register are written by the PCI interface. This bit operates as read or write one clear. A write to
this bit with the data of one will cause this bit to be reset; a write to this bit with the data as zero
will not change the state of this bit.
15
Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the
read transfer count reaches zero. This bit is read/write.
14
Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the write
transfer count reaches zero. This bit is read/write.
13
Reserved. Always zero.
12
Enable outgoing mailbox interrupt. This bit allows a read by the PCI of the outgoing mailbox register
identified by bits 11 through 8 to produce an Add-On interface interrupt. This bit is read/write.
11:10
Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes is to be
the source for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects
mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.
9:8
Outgoing Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by
bits 11 and 10 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1,
[10]b selects byte 2, and [11]b selects byte 3. This field is read/write.
7:5
Reserved. Always zero.
Bit
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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