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參數(shù)資料
| 型號(hào)： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標(biāo)設(shè)備的32位 |
| 文件頁(yè)數(shù)： | 6/190頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | S5935 |
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10. FIFO OVERVIEW...............................................................................................................................10-117
Functional Description .....................................................................................................................10-117
FIFO Buffer Management and Endian Conversion ..............................................................10-117
FIFO Advance Conditions.....................................................................................................10-117
Endian Conversion ...............................................................................................................10-118
64-Bit Endian Conversion.....................................................................................................10-119
Add-On FIFO Status Indicators ........................................................................................... 10-120
Add-On FIFO Control Signals.............................................................................................. 10-120
PCI Bus Mastering with the FIFO ........................................................................................ 10-120
Add-On Initiated Bus Mastering........................................................................................... 10-120
PCI Initiated Bus Mastering ................................................................................................. 10-121
Address and Transfer Count Registers ............................................................................... 10-121
Bus Mastering FIFO Management Schemes ...................................................................... 10-121
FIFO Bus Master Cycle Priority ........................................................................................... 10-122
FIFO Generated Bus Master Interrupts ............................................................................... 10-122
Bus Interface................................................................................................................................... 10-122
FIFO PCI Interface (Target Mode) ....................................................................................... 10-122
FIFO PCI Interface (Initiator Mode) ..................................................................................... 10-123
FIFO PCI Bus Master Reads............................................................................................... 10-125
FIFO PCI Bus Master Writes ............................................................................................... 10-125
Add-On Bus Interface .......................................................................................................... 10-125
Add-On FIFO Register Accesses ........................................................................................ 10-125
Add-On FIFO Direct Access Mode ...................................................................................... 10-126
Additional Status/Control Signals for Add-On Initiated Bus Mastering ................................ 10-127
FIFO Generated Add-On Interrupts ..................................................................................... 10-128
8-Bit and 16-Bit FIFO Add-On Interfaces............................................................................. 10-128
Configuration................................................................................................................................... 10-129
FIFO Setup During Initialization........................................................................................... 10-129
FIFO Status and Control Bits............................................................................................... 10-129
PCI Initiated FIFO Bus Mastering Setup ............................................................................. 10-130
Add-On Initiated FIFO Bus Mastering Setup ....................................................................... 10-131
11. PASS-THRU OVERVIEW ..................................................................................................................11-133
Functional Description .....................................................................................................................11-133
Pass-Thru Transfers .............................................................................................................11-133
Pass-Thru Status/Control Signals ........................................................................................11-134
Pass-Thru Add-On Data Bus Sizing .....................................................................................11-134
Bus Interface....................................................................................................................................11-134
PCI Bus Interface .................................................................................................................11-134
PCI Pass-Thru Single Cycle Accesses.................................................................................11-134
PCI Pass-Thru Burst Accesses ............................................................................................11-134
PCI Retry Conditions ............................................................................................................11-134
PCI Write Retries ..................................................................................................................11-134
PCI Read Retries..................................................................................................................11-136
Add-On Bus Interface ...........................................................................................................11-136
Single Cycle Pass-Thru Writes .............................................................................................11-136
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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