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參數(shù)資料
| 型號： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標設備的32位 |
| 文件頁數(shù)： | 42/190頁 |
| 文件大?。?/td> | 748K |
| 代理商： | S5935 |
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3-34
S5935
PCI CONFIGURATION REGISTERS
BASE ADDRESS REGISTERS (BADR)
Register Name:
Address Offset:
Power-up value:
Base Address
10h, 14h, 18h, 1Ch, 20h, 24h
FFFFFFC1h for offset 10h;
00000000h for all others
External nvRAM offset
050h, 54h, 58h, 5Ch, 60h
(BADR0-4)
high bits Read/Write; low bits
Read Only
32 bits
Boot-load:
Attribute:
Size:
The base address registers provide a mechanism for
assigning memory or I/O space for the Add-On func-
tion. The actual location(s) the Add-On function is to
respond to is determined by first interrogating these
registers to ascertain the size or space desired, and
then writing the high-order field of each register to
place it physically in the system’s address space. Bit
zero of each field is used to select whether the space
required is to be decoded as memory (bit 0 = 0) or I/O
(bit 0 = 1). Since this PCI controller has 16 DWORDs
of internal operating registers, the Base Address
Register at offset 10h is assigned to them. The re-
maining five base address registers can only be used
by boot-loading them from the external nvRAM inter-
face. BADR5 register is not implemented and will re-
turn all 0’s.
Determining Base Address Size
The address space defined by a given base address
register is determined by writing all 1s to a given
base address register from the PCI bus and then
reading that register back. The number of 0s returned
starting from D4 for memory space and D2 for I/O
space toward the high-order bits reveals the amount
of address space desired. Tables 23 and 24 list the
possible returned values and their corresponding size
for both memory and I/O, respectively. Included in
the table are the nvRAM/EPROM boot values which
correspond to a given assigned size. A register re-
turning all zeros is disabled.
Assigning the Base Address
After a base address has been sized as described in
the preceding paragraph, the region associated with
that base address register (the high order one bits)
can physically locate it in memory (or I/O) space. For
example, the first base address register returns
FFFFFFC1h indicating an I/O space (D0=1) and is
then written with the value 00000300h. This means
that the controller’s internal registers can be selected
for I/O addresses between 00000300h through
0000033Fh, in this example. The base address value
must be on a natural binary boundary for the required
size (example 300h, 340h, 380h etc.; 338h would not
be allowable).
Figure 11b. Base Address Register — I/O
Figure 11a. Base Address Register — Memory
31
0
X
1
0
2
Bit
Value
I/O Space
Indicator (RO)
Reserved (RO)
Programmable (R/W)
31 30 29
0
X
1
X
2
X
3
X
4
See page 3-157
}
Bit
Value
Memory Space
Indicator (RO)
Type (RO)
00-locate anywhere (32)
01-below 1 MB
10-locate anywhere (64)
11-reserved
Prefetchable (RO)
0 = Memory
1 = I/O
Programmable (R/W)
相關PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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