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參數(shù)資料
| 型號： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標設(shè)備的32位 |
| 文件頁數(shù)： | 104/190頁 |
| 文件大?。?/td> | 748K |
| 代理商： | S5935 |
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7-96
PCI BUS INTERFACE
S5935
Bus Acquisition
Once GNT# is asserted, giving bus ownership to the
S5935, the S5935 must wait until the PCI bus be-
comes idle. This delay is called bus acquisition la-
tency and involves the state of the signals FRAME#
and IRDY#. The current bus master must complete
its current transaction before the S5935 may drive
the bus. Table 3 depicts the four possible combina-
tions of FRAME# and IRDY# with their interpretation.
Target Latency
The PCI specification requires that a selected target
relinquish the bus should an access to that target
require more than eight PCI clock periods (16 clocks
for the first data phase in a burst). Slow targets can
exist within the PCI specification by using the target
initiated retry. This prevents slow target devices from
potentially monopolizing the PCI bus and also allows
more accurate estimations for bus access latency.
Target Locking
It is possible for a PCI bus master to obtain exclusive
access to a target (“l(fā)ocking”) through use of the PCI
bus signal LOCK#. LOCK# is different from the other
PCI bus signals because its ownership may belong to
any bus master, even if it does not currently have
ownership of the PCI bus. The ownership of LOCK#,
if not already claimed by another master, may be
achieved by the current PCI bus master on the clock
period following the initial assertion of FRAME#. Fig-
ure 15 describes the signal relationship for establish-
ing a lock. The ownership of LOCK#, once
established, persists even while other bus masters
control the bus. Ownership can only be relinquished
by the master which originally established the lock.
Table 3. Possible Combinations of FRAME# and IRDY#
FRAME#
IRDY#
Description
deasserted
deasserted
Bus Idle
deasserted
asserted
The initiator is ready to complete the last data transfer
of a transaction.
asserted
deasserted
An Initiator has a transaction in progress but is not able
to complete the data transfer on this clock.
asserted
asserted
An initiator has a transaction in progress and is able to
complete a data transfer.
Figure 15. Engaging the LOCK# Signal
PCI CLOCK
FRAME #
LOCK #
AD[31:0]
IRDY#
TRDY#
DEVSEL#
ADDRESS
DATA
1
2
3
4
5
TARGET
BECOMES
LOCKED
LOCK
MECHANISM
AVAILABLE
UPON FIRST
ACCESS
LOCK MECHANISM
AVAILABLE
LOCK ESTABLISHED
LOCK MAINTAINED
BUS
IDLE
STILL DRIVEN BY PREVIOUS
OWNER (TARGET IS LOCKED)
6
(T)
(T)
(T)
(I)
(I)
(I)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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