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參數(shù)資料
| 型號： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標(biāo)設(shè)備的32位 |
| 文件頁數(shù)： | 119/190頁 |
| 文件大?。?/td> | 748K |
| 代理商： | S5935 |
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MAILBOX OVERVIEW
S5935
If the S5935 is programmed to generate a PCI inter-
rupt (INTA#), on an Add-On write to outgoing mailbox
4, byte 3, a rising edge on EMBCLK generates a PCI
interrupt. The bits EMB7:0 can be read by the PCI
bus interface by reading the PCI incoming mailbox 4,
byte 3. These bits are useful to indicate various con-
ditions which may have caused the interrupt.
When using the S5935 with a byte-wide boot device,
the capability to generate PCI interrupts with Add-On
hardware does not exist. In this configuration, PCI
incoming mailbox 4, byte 3 (Add-On incoming mail-
box 4, byte 3) cannot be used to transfer data from
the Add-On - it always returns zeros when read from
the PCI bus. This mailbox byte is sacrificed to allow
the added functionality provided when a byte-wide
boot device is not used.
BUS INTERFACE
The mailboxes appear on the Add-On and PCI bus
interfaces as eight operation registers. Four are out-
going mailboxes, four are incoming mailboxes. The
mailboxes may be used to generate interrupts to
each of the interfaces. The following sections de-
scribe the Add-On and PCI bus interfaces for the
mailbox registers.
PCI Bus Interface
The mailboxes are only accessible with the S5935 as
a PCI target. The mailbox operation registers do not
support burst accesses by an initiator. A PCI initiator
attempting to burst to the mailbox registers causes the
S5935 to respond with a target disconnect with data.
PCI writes to full outgoing mailboxes overwrite data
currently in that the mailbox. PCI reads from empty
incoming mailboxes return the data that was previ-
ously contained in the mailbox. Neither of these situa-
tions cause a target retry or abort.
PCI incoming and outgoing mailbox interrupts are en-
abled in the Interrupt Control/Status Register
(INTCSR). The mailboxes can generate a PCI inter-
rupt (INTA#) under two conditions (individually en-
abled). For an incoming mailbox full interrupt, INTA#
is asserted on the PCI clock rising edge after the
Add-On mailbox write completes. For an outgoing
mailbox empty interrupt, INTA# is asserted on the
PCI clock rising edge after the Add-On mailbox read
completes (the rising edge of RD#). INTA# is
deasserted on the next PCI clock rising edge after
the PCI access to clear the mailbox interrupt com-
pletes (TRDY# deasserted).
Add-On Bus Interface
The Add-On mailbox interface behaves similar to the
PCI bus interface. Add-On writes to full outgoing
mailboxes overwrite data currently in that mailbox.
PCI reads from empty incoming mailboxes return the
data that was previously contained in the mailbox.
Add-On incoming and outgoing mailbox interrupts are
enabled in the Add-On Interrupt Control/Status Reg-
ister (AINT). The mailboxes can generate the Add-On
IRQ# interrupt under two conditions (individually en-
abled). For an incoming mailbox full interrupt, IRQ# is
asserted one PCI clock period after the PCI mailbox
write completes (TRDY# deasserted). For an outgo-
ing mailbox empty interrupt, IRQ# is asserted one
PCI clock period after the PCI mailbox read com-
pletes (TRDY# deasserted). IRQ# is deasserted im-
mediately when the Add-On clears the mailbox
interrupt.
When the S5935 is used with a serial nv memory boot
device or no external boot device, the device pins
EA8:0 are redefined. EA7:0 become EMB7:0 data in-
puts and EA8 becomes EMBCLK, a load clock. This
configuration allows the Add-On to generate PCI inter-
rupts with a low-to-high transition on EMBCLK. The
PCI incoming mailbox interrupt must be enabled and
set for mailbox 4, byte3 in the PCI Interrupt Control/
Status Register (INTCSR). EMBCLK should begin
high and be pulsed low, then high to be recognized.
The rising edge of EMBCLK generates the interrupt.
The rising edge of EMBCLK also latches in the values
on EMB7:0. The S5935 interrupt logic must be cleared
(INTA# deasserted) through INTCSR before further
EMBCLK interrupts are recognized.
8-Bit and 16-Bit Add-On Interfaces
Some Add-On designs may implement an 8-bit or 16-
bit bus interface. The mailboxes do not require a 32-
bit Add-On interface. For 8-bit interfaces, the 8-bit
data bus may be externally connected to all four
bytes of the 32-bit Add-On interface (DQ 31:24,
23:16, 15:8, 7:0 are all connected). The Add-On de-
vice reading or writing the mailbox registers may ac-
cess all mailbox bytes by cycling through the Add-On
byte enable inputs. A similar solution applies to 16-bit
Add-On buses. This solution works for Add-Ons
which always use just 8-bit or just 16-bit accesses.
If the MODE pin is high, indicating a 16-bit Add-On
interface, the previous solution may be modified for an
8-bit interface. The difference is that ADR1 must be
toggled after the first two accesses to steer the S5935
internal data bus to the upper 16-bits of the mailboxes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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