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參數(shù)資料
| 型號(hào)： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標(biāo)設(shè)備的32位 |
| 文件頁(yè)數(shù)： | 133/190頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | S5935 |
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10-125
FIFO OVERVIEW
S5935
FIFO PCI Bus Master Reads
For PCI read transfers (filling the PCI to Add-On
FIFO), read cycles are performed until one of the
following occurs:
– Bus Master Read Transfer Count Register
(MRTC), if used, reaches zero
– The PCI to Add-On FIFO is full
– GNT# is removed by the PCI bus arbiter
– AMREN is deasserted
If the transfer count is not zero, GNT# remains as-
serted, and AMREN is asserted, the FIFO continues
to read data from the PCI bus until there are no
empty locations in the PCI to Add-On FIFO. If the
Add-On can empty the FIFO as quickly as it can be
filled from the PCI bus, very long bursts are possible.
The S5935 deasserts REQ# when it completes the
access to fill the last location in the FIFO. Once
REQ# is deasserted, it will not be reasserted until the
FIFO management condition is met.
FIFO PCI Bus Master Writes
For PCI write transfers (emptying the Add-On to PCI
FIFO), write cycles are performed until one of the
following occurs:
– Bus Master Write Transfer Count Register
(MWTC), if used, reaches zero
– The Add-On to PCI FIFO is empty
– GNT# is removed by the PCI bus arbiter
– AMWEN is deasserted
If the transfer count is not zero, GNT# remains as-
serted, and AMWEN is asserted, The FIFO continues
to write data to the PCI bus until there are is no data in
the Add-On to PCI FIFO. If the Add-On can fill the FIFO
as quickly as it can be emptied to the PCI bus, very
long bursts are possible. The S5935 deasserts REQ#
when it completes the access to transfer the last data in
the FIFO. Once REQ# is deasserted, it will not be reas-
serted until the FIFO management condition is met.
Add-On Bus Interface
The FIFO register may be accessed in two ways from
the Add-On interface. It can be accessed through
normal register accesses or directly with the
RDFIFO# and WRFIFO# inputs. In addition, the FIFO
register can also be accessed synchronous to
BPCLK. The Add-On interface also supports
datapaths which are not 32-bits. The method used to
access the FIFO from the Add-On interface is inde-
pendent of whether the FIFO is a PCI PCI target or a
PCI initiator.
Add-On FIFO Register Accesses
The FIFO may be accessed from the Add-On interface
through the Add-On FIFO Port Register (AFIFO) read
or write. This is offset 20h in the Add-On Operation
Registers. This register is accessed synchronous to
BPCLK. To access the FIFO as a normal Add-On Op-
eration Register, ADR[6:2], BE[3:0]#, SELECT#, and
RD# or WR# are required.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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