
10-127
FIFO OVERVIEW
S5935
Additional Status/Control Signals for Add-On
Initiated Bus Mastering
If a serial non-volatile memory is used to configure the
S5935, and the device is configured for Add-On initi-
ated bus mastering, two additional FIFO status signals
and four additional control signals are available to the
Add-On interface. The FRF and FWE outputs provide
additional FIFO status information. Inputs FRC#,
FWC#, AMREN, and AMWEN provide additional FIFO
control. Applications may use these signals to monitor/
control FIFO flags and PCI bus requests. These new
signals are some of the lines that were used for byte-
wide nvram interface, but now are reconfigured. The
reconfigured lines are as follows:
Outputs:
E_ADDR (15)
FIFO Read Full: Indicates that the PCI to Add-On
FIFO is full.
FRF
E_ADDR (14)
FIFO Write Empty: Indicates the last Add-On to PCI
FIFO . Data has transferred to a final buffer and is
queued for transfer, FIFO is empty.
FWE
Inputs:
EQ (7)
Add-On bus Mastering Write ENable: This input is
driven high to enable bus master writes.
AMWEN
EQ (6)
Add-On bus Mastering Read ENable: This input is
driven high to enable bus master reads.
AMREN
EQ (5)
FIFO Read Clear: This line is driven low to clear the
PCI to Add-On FIFO.
FRC#
EQ (4)
FIFO Write Clear: This line is driven low to clear the
Add-On to PCI FIFO.
FWC#
FRF (PCI to Add-On FIFO full) and FWE (Add-On to
PCI FIFO empty) supplement the RDEMPTY and
WRFULL status indicators. These additional status
outputs provide additional FIFO status information for
Add-On FIFO control logic.
Figure 8. Synchronous FIFO Register Burst RDFIFO# Access Example
BPCLK
DQ[31:0]
RDFIFO#
RDEMPTY
Data 1
Data 2
Data 0
FIFO Pointer Advances
Status Before Read
New Status
New Status