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參數(shù)資料
| 型號(hào)： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標(biāo)設(shè)備的32位 |
| 文件頁(yè)數(shù)： | 12/190頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | S5935 |
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1-4
ARCHITECTURAL OVERVIEW
S5935
P
Mailbox Status Register
S5935
A
PCI MB1
Byte 0
PCI MB2
Byte 0
PCI MB3
Byte 0
PCI MB4
Byte 0
PCI MB1
Byte 1
PCI MB2
Byte 1
PCI MB3
Byte 1
PCI MB4
Byte 1
PCI MB1
Byte 2
PCI MB2
Byte 2
PCI MB3
Byte 2
PCI MB4
Byte 2
PCI MB1
Byte 3
PCI MB2
Byte 3
PCI MB3
Byte 3
PCI MB4
Byte 3
Add MB1
Byte 0
Add MB2
Byte 0
Add MB3
Byte 0
Add MB4
Byte 0
Add MB1
Byte 1
Add MB2
Byte 1
Add MB3
Byte 1
Add MB4
Byte 1
Add MB1
Byte 2
Add MB2
Byte 2
Add MB3
Byte 2
Add MB4
Byte 2
Add MB1
Byte 3
Add MB2
Byte 3
Add MB3
Byte 3
Add MB4
Byte 3
Mailbox Operation
The Mailbox Registers are divided into two four DWORD
sets. Each set is dedicated to one bus for transferring
data to the other bus. Figure 3 below shows a block
diagram of the mailbox section of the S5935. The
provision of Mailbox Registers provides an easy path
for the transfer of user information (command, status or
parametric data) between the two buses. An empty/full
indication for each Mailbox Register, at the byte level, is
determined by polling a Status Register accessible to
both the PCI and Add-On buses. Providing Mailbox byte
level empty/full indications allows for greater flexibility in
8-, 16- or 32-bit system interfaces. i.e., transferring a
single byte to an 8-bit Add-On bus without requiring the
assembling or disassembling of 32-bit data.
The generation of interrupts from Mailbox Registers is
equivalent with the commonly known ‘DOORBELL’
interrupt technique. Bit locations configured within the
S5935’s Operation Registers select a Mailbox and
Mailbox byte which is to generate an interrupt when full
or touched. A mailbox interrupt control register is then
used to enable interrupt generation and to select if the
interrupt is to be generated on the PCI or Add-On Local
bus. PCI Local bus interrupts may also be generated
from direct hardware interfacing due to a unique AMCC
feature. A dedicated Mailbox byte is directly accessible
via a set of hardware device signal pins. A mailbox load
signal pin latches Add-On bus data directly into the
Mailbox initiating a PCI bus interrupt if enabled. Mailbox
data may also be read in a similar manner. This option
is shared with the byte wide non-volatile memory signal
pins. The S5935 must use the serial nvRAM for the
direct mailbox option signal pins to be available or they
are assigned to the byte wide at power up.
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5
Table 3. Add-On Bus Operation Registers
Figure 3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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