- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374668 > S5935 (Applied Micro Circuits Corp.) PCI 5V Bus Master/Target Device 32-bit PDF資料下載
參數(shù)資料
| 型號： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標(biāo)設(shè)備的32位 |
| 文件頁數(shù)： | 149/190頁 |
| 文件大?。?/td> | 748K |
| 代理商： | S5935 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁當(dāng)前第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁
11-141
PASS-THRU OVERVIEW
S5935
PTBURST#
Asserted. The access has a
multiple data phases.
PTNUM[1:0] 01. Indicates the PCI access
was to Pass-Thru region 1.
PTWR
Asserted. The Pass-Thru
access is a write.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
Clock 3:
SELECT#, byte enables, and the address
inputs remain driven to read the Pass-Thru
Data Register at offset 2Ch. RD# is
asserted to drive data register contents
onto the DQ bus.
Clock 4:
Add-On logic uses the rising edge of clock 4
to store DATA 1 from the S5935. PTRDY#
asserted at the rising edge of clock 4
completes the current data phase. DATA 2
is driven on the Add-On bus.
Clock 5:
Add-On logic uses the rising edge of clock 5
to store DATA 2 from the S5935. PTRDY#
asserted at the rising edge of clock 5
completes the current data phase. DATA 3
is driven on the Add-On bus.
Clock 6:
Add-On logic uses the rising edge of clock 6
to store DATA 3 from the S5935. PTRDY#
asserted at the rising edge of clock 6
completes the current data phase. On the
PCI bus, IRDY# has been deasserted,
causing PTATN# to be deasserted. This is
how a PCI initiator adds wait states, if it
cannot provide data quickly enough. Data
on the Add-On bus is not valid.
Clock 7:
Because PTATN# remains deasserted,
Add-On logic cannot store data at the
rising edge of clock 7. PTATN# is reas-
serted, indicating the PCI initiator is no
longer adding wait states. DATA 4 is driven
on the Add-On bus.
Clock 8:
Add-On logic uses the rising edge of clock 8
to store DATA 4 from the S5935. PTRDY#
asserted at the rising edge of clock 8
completes the current data phase. On the
PCI bus, IRDY# has been deasserted
again, causing PTATN# to be deasserted.
Data on the Add-On bus is not valid.
Clock 9:
The PCI initiator is still adding wait states.
Add-On logic cannot store data while
PTATN# is deasserted.
Clock 10:
Because PTATN# remains deasserted,
Add-On logic cannot read data at the rising
edge of clock 10. PTATN# is reasserted,
indicating the PCI initiator is no longer
adding wait states. DATA 5 is driven on the
Add-On bus.
Clock 11:
Add-On logic uses the rising edge of clock
11 to store DATA 5 from the S5935.
PTRDY# asserted at the rising edge of
clock 11 completes the current data phase.
DATA 6 is driven on the Add-On bus.
Clock 12:
Add-On logic uses the rising edge of clock
12 to store DATA 6 from the S5935.
PTRDY# asserted at the rising edge of
clock 12 completes the final data phase
Clock 13:
PTATN# and PTBURST# deasserted at
the rising edge of clock 13 indicates the
Pass-Thru access is complete. The S5935
can accept new Pass-Thru accesses from
the PCI bus at clock 15.
Figure 5 also shows a 5 data phase Pass-Thru burst
write, but the Add-On logic uses PTRDY# to control
the rate at which data is transferred. In many applica-
tions, Add-On logic is not fast enough to accept data
at every BPCLK rising edge (every 30 ns in a 33 MHz
PCI system). In this example, the Add-On interface
accepts data every other clock. In the example, RD#
is asserted during the entire Add-On burst, but it can
be deasserted when PTRDY# is deasserted, the
S5935 functions the same under both conditions.
Clock 0:
PCI address information is stored in the
S5935 Pass-Thru Address Register.
Clock 1:
The PCI address is recognized as an
access to Pass-Thru region 1. PCI data for
the first data phase is stored in the S5935
Pass-Thru Data Register. PTATN# is
asserted by the S5935 to indicate a Pass-
Thru access is occurring.
Clock 2:
Pass-Thru status signals indicate what
action is required by Add-On logic. Pass-
Thru status outputs are valid when
PTATN# is active and are sampled by the
Add-On at the rising edge of clock 2.
PTBURST#
Asserted. The access has
multiple data phases.
PTNUM[1:0] 01. Indicates the PCI access
is to Pass-Thru region 1.
PTWR
Asserted. The Pass-Thru
access is a write.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
The PTADR# input is asserted to read the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。