- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374668 > S5935 (Applied Micro Circuits Corp.) PCI 5V Bus Master/Target Device 32-bit PDF資料下載
參數(shù)資料
| 型號(hào)： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標(biāo)設(shè)備的32位 |
| 文件頁數(shù)： | 23/190頁 |
| 文件大小： | 748K |
| 代理商： | S5935 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁
2-15
SIGNAL DESCRIPTIONS
S5935
FIFO Access Pins
Signal
Type
Description
WRFIFO#
in
Write FIFO. This signal provides a method to directly write the FIFO without having to
generate the SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO.
Access width is either 32 bits or 16 bits depending on the data bus size available.
This signal is intended for implementing PCI DMA transfers with the Add-On system.
RDFIFO#
in
Read FIFO. This signal provides a method to directly read the FIFO without having to
generate the SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO.
Access width is either 32 bits or 16 bits, depending on the data bus size defined by
the MODE pin. This signal is intended for implementing PCI DMA transfers with the
Add-On system.
WRFULL
out
Write FIFO full. This pin indicates whether the Add-On-to-PCI bus FIFO is able to
accept more data. This pin is intended to be used to implement DMA hardware on
the Add-On system bus. A logic low output from this pin can be used to represent a
DMA write (Add-On to-PCI FIFO) request.
RDEMPTY
out
Read FIFO Empty. This pin indicates whether the read FIFO (PCI-to-Add-On FIFO)
contains data. This pin is intended to be used by the Add-On system to control DMA
transfers from the PCI bus to the Add-On system bus. A logic low from this pin can
be used to represent a DMA (PCI-to-Add-On FIFO) request.
Pass-Thru Interface Pins
Signal
Type
Description
PTATN#
out
Pass-Thru Attention. This signal identifies that an active PCI bus cycle has been
decoded and data must be read from or written to the Pass-Thru Data Register.
PTBURST#
out
Pass-Thru Burst. This signal identifies PCI bus operations involving the current Pass-
Thru cycle as requesting burst access.
PTRDY#
in
Pass-Thru Ready. This input indicates when Add-On logic has completed a Pass-
Thru cycle and another may be initiated.
PTNUM[1:0]
out
Pass-Thru Number. These signals identify which of the four base address registers
decoded a Pass-Thru bus activity. These bits are only meaningful when signal
PTATN# is active. A value of 00 corresponds to Base Address Register 1, a value of
01 for Base Address Register 2, and so on.
PTBE[3:0]#
out
Pass-Thru Byte Enables. These signals indicate which bytes are requested for a given
Pass-Thru operation. They are valid during the presence of signal PTATN# active.
PTADR#
in
Pass-Thru Address. This signal causes the actual Pass-Thru requested address to
be presented as outputs on the DQ pins DQ[31:0] for Add-Ons with 32-bit buses, or
the low-order 16 bits for Add-Ons with 16-bit buses. It is necessary that all other bus
control signals be in their inactive state during the assertion of PTADR#. The purpose
of this signal is to provide the direct addressing of external Add-On peripherals
through use of the PTNUM[1:0] and the low-order address bits presented on the DQ
bus with this pin active.
PTWR
out
Pass-Thru Write. This signal identifies whether a Pass-Thru operation is a read or
write cycle. This signal is valid only when PTATN# is active.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。