參數(shù)資料
型號(hào): S5935
廠商: Applied Micro Circuits Corp.
英文描述: PCI 5V Bus Master/Target Device 32-bit
中文描述: 5V的的PCI總線主/目標(biāo)設(shè)備的32位
文件頁數(shù): 21/190頁
文件大?。?/td> 748K
代理商: S5935
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁
2-13
SIGNAL DESCRIPTIONS
S5935
NON-VOLATILE MEMORY INTERFACE SIGNALS
This signal grouping provides for connection to external non-volatile memories. Either a serial or byte-wide device
may be used.
The serial interface shares the read and write control pins used for interfacing with byte-wide memory devices. Since
it is intended that only one (serial or byte wide) configuration be used in any given implementation, separate
descriptions are provided for each. The S5935 provides the pins necessary to interface to a byte wide non-volatile
memory. When they are connected to a properly configured serial memory, these byte wide interface pins assume
alternate functions. These alternate functions include added external FIFO status flags, FIFO reset control, Add-On
control for bus mastering and a hardware interface mailbox port.
Byte-Wide nv Devices
Signal
Type
Description
SCL
t/s
Serial Clock. This output is intended to drive a two-wire Serial Interface and functions
as the bus’s master. It is intended that this signal be directly connected to one or
more inexpensive serial non-volatile RAMs or EEPROMs. This pin is shared with the
byte wide interface signal, ERD#.
SDA
t/s
Serial Data/Address. This bidirectional pin is used to transfer addresses and data to or from
a serial nvRAM or EEPROM. It is an open drain output and intended to be wire-ORed
with all other devices on the serial bus using a 4.7K external pull-up resistor. This pin
is shared with the byte wide interface signal, EWR#.
SNV
in
Serial Non-Volatile Device. This input, when high, indicates a serial boot device or no
boot device is present. When this pin is low, a byte-wide boot device is present.
Note: SCL and SDA are not controlled by FLT#.
Serial nv Devices
Signal
Type
Description
EA[15:00]
t/s
External nv memory address. These signals connect directly to the external BIOS (or
EEPROM) or EPROM address pins EA0 through EA15. The PCI interface controller
assembles 32-bit-wide accesses through multiple read cycles of the 8-bit device. The
address space from 0040h through 007Fh is used to preload and initialize the PCI
configuration registers. Should an external nv memory be used, the minimum size
required is 128 bytes and the maximum is 64K bytes. When a serial memory is
connected to the S5935, the pins EA[7:0] are reconfigured to become a hardware Add-
On to PCI mailbox register with the EA8 pin as the mailbox load clock. Also, the EA15
signal pin will provide an indication that the PCI to Add-On FIFO is full (FRF#), and the
EA14 signal pin will indicate whether the Add-On to PCI FIFO is empty (FWE#).
ERD#
out
External nv memory read control. This pin is asserted during read operations involv-
ing the external non-volatile memory. Data is transferred into the S5935 during the
low to high transition of ERD#. This pin is shared with the serial external memory
interface signal, SCL.
EWR#
t/s
External nv memory write control. This pin is asserted during write operations involv-
ing the external non-volatile memory. Data is presented on pins EQ[7:0] along with its
address on pins EA[15:0] throughout the entire assertion of EWR#. This pin is shared
with the serial external memory interface signal, SDA.
EQ[7:0]
t/s
External memory data bus. These pins are used to directly connect with the data pins
of an external non-volatile memory. When a serial memory is connected to the
S5935, the pins EQ4, EQ5, EQ6 and EQ7 become reconfigured to provide signal
pins for bus mastering control from the Add-On interface.
相關(guān)PDF資料
PDF描述
S5935QF PCI 5V Bus Master/Target Device 32-bit
S5990-01 POSITION SENSITIVE DETECTOR
S5629-01 POSITION SENSITIVE DETECTOR
S5629-02 POSITION SENSITIVE DETECTOR
S5991-01 POSITION SENSITIVE DETECTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S5935_07 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product
S59355QRC 制造商:AppliedMicro 功能描述:
S5935QF 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product
S5935QRC 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP
S5935TF 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit