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參數(shù)資料
| 型號(hào)： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標(biāo)設(shè)備的32位 |
| 文件頁(yè)數(shù)： | 158/190頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | S5935 |
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11-150
PASS-THRU OVERVIEW
S5935
To write data into the APTD Register, the PTBEn#
output and the BEn# input must both be asserted.
The following describes how APTD Register writes
are controlled:
Write BYTE3 if PTBE3# AND BE3# are asserted
Write BYTE2 if PTBE2# AND BE2# are asserted
Write BYTE1 if PTBE1# AND BE1# are asserted
Write BYTE0 if PTBE0# AND BE0# are asserted
After each byte is written into the Pass-Thru data
register, its corresponding PTBE[3:0]# output is
deasserted. This allows Add-On logic to monitor
which bytes have been written, and which bytes re-
main to be written. When all bytes requested by the
PCI initiator have been written, the PTBE[3:0]# are all
be deasserted, and the Add-On asserts PTRDY#.
Figure 11 shows Pass-Thru operation for a region
defined for an 8-bit Add-On bus interface. As the 8-bit
device is connected only to DQ[7:0], the device must
access APTD one byte at a time.
The PCI initiator has performed a 32-bit write of
08D49A30h to Pass-Thru region zero. PTBE[3:0]#
are all asserted. At clock 1, the Add-On begins read-
ing the APTD Register (asserting SELECT#,
ADR[6:2], and RD#). Add-On logic asserts BE0#, and
BYTE0 of APTD is driven on DQ[7:0]. At the rising
edge of clock 2, BE0# is sampled by the S5935 and
PTBE0# is deasserted. PTBE[3:1]# are still asserted.
During clock 2, only BE1# is activated, and BYTE1 of
APTD is driven on DQ[7:0]. At the rising edge of
clock 3, BE1# is sampled by the S5935 and PTBE1#
is deasserted. PTBE[3:2]# are still asserted.
This process continues until all bytes have been read
from the APTD Register. During clock 5, RD# is
deasserted and PTRDY# is asserted. PTRDY# is
sampled by the S5935 at the rising edge of clock 6,
and the current data phase is completed. PTATN# is
deasserted and new data can be written from the PCI
bus. In this example, the byte enables are asserted,
sequentially, from BE0# to BE3#. This is not re-
quired, bytes may be accessed in any order.
New data is written by the PCI initiator and is avail-
able in the APTD Register during clock 7. RD# is
asserted and the byte enables are cycled again. With
each new data from the PCI bus, the Add-On se-
quences through the byte enables to access APTD
via DQ[7:0].
For 16-bit peripheral devices, the byte steering works
in the same way. Because the Add-On data bus is
16-bits wide, only two 16-bit cycles are required to
access the entire APTD Register. Two byte enables
can be asserted during each access.
In Figure 11, RD# is held low and the byte enables
are changed each clock. This assumes the Add-On
can accept data at one byte per clock. This is the
fastest transfer possible. For slower devices, wait
states may be added.
As long as the byte enables remain in a given state,
the corresponding byte of the APTD Register is con-
nected to the DQ bus (the RD# or WR# pulse may
also be lengthened). Each access may be extended
for slower Add-On devices, but extending individual
data phases for Pass-Thru cycles may result in the
S5935 requesting retries by the initiator.
10
11
12
13
9
8
7
6
5
4
3
2
3Ch
3Ch
2Ch
Fh
0h
1h
3h
7h
Fh
0h
1h
3h
7h
Fh
1
BPCLK
PTATN#
PTWR
PTBE[3:0]#
PTNUM[1:0]
PTBURST#
Fh
Bh
Eh
Dh
7h
Fh
Eh
Dh
Bh
7h
Fh
D4h
30h
9Ah
08h
DDh
CCh
BBh
AAh
ADDR
0
SELECT#
BE[3:0]#
PTADR#
PTRDY#
ADR[6:2]
RD#
DQ[7:0]
Figure 11. Pass-Thru Write to an 8-bit Add-On Device
Note: 8 Bit Mode BE’s are E, D, B, 7; 16 Bit Mode BE’s are C, 3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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