參數(shù)資料
型號: P95020NQG8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 電源管理
英文描述: 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝: 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù): 92/169頁
文件大小: 4297K
代理商: P95020NQG8
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
29
2011 Integrated Device Technology, Inc.
Implementation generally takes the form:
[]
[]2
n
y
0
a
2
a
1
n
y
0
a
1
a
2
n
x
0
a
2
b
1
n
x
0
a
1
b
n
x
0
a
0
b
n
y
+
+
=
(3)
It can be seen that 5 coefficients are needed, and if a0 is
set to 1 then only b0, b1, b2, a1, and a2 are needed. To
compensate for the total gain realized from all 5 bands the
EQ amplitude is adjusted to prevent saturation. Each
channel has an inverse gain coefficient that is used to
compensate for the gain in the EQ bands. So, for 5
bands/channel with 5 coefficients/band + inverse
gain/channel, there are a total of 52 values needed.
These values are pre-calculated and programmed into
RAM before use. The default values should be benign
such as an all-pass implementation, but it is permissible to
implement other transfer functions.
Software Requirements
The EQ must be programmed before enabling (bypass
turned off). {Coefficients are random at power-on.}
When changing coefficients, the EQ must be bypassed
before programming. Muting the path is not sufficient and
may not prevent issues. Changing coefficients while the
filter is in use may cause stability issues, clicks and pops,
or other problems.
All coefficients are calculated by software. Software must
verify amplifier stability.
Programming incorrect
coefficients can cause oscillation, clipping, or other
undesirable effects.
After calculating coefficients,
software must calculate the inverse gain (normalize the
response) for each channel (Left and Right) to prevent
saturation or inadequate output levels. All values are then
either programmed directly into the device or stored in a
table for use in a configuration file or firmware.
Audio – Class D Registers
The Audio Class-D Module can be controlled and monitored by writing 8-bit control words to the various Registers.
The Base addresses are defined in Table 11 – Register Address Global Mapping on Page 16.
Class D – RESERVED Registers
These registers are reserved. Do not write to them.
IC Address = Page-2: 26(0x1A), C Address = 0xA21A
IC Address = Page-2: 27(0x1B), C Address = 0xA21B
IC Address = Page-2: 37(0x25), C Address = 0xA225
IC Address = Page-2: 47(0x2F), C Address = 0xA22F
IC Address = Page-2: 49(0x31), C Address = 0xA231
thru Page-2: 53(0x35), C Address = 0xA235
IC Address = Page-2: 64(0x40), C Address = 0xA240
thru Page-2: 255(0xFF), C Address = 0xA2FF
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