參數(shù)資料
型號(hào)： P95020NQG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù)： 41/169頁
文件大?。?/td> 4297K
代理商： P95020NQG8
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
135
2011 Integrated Device Technology, Inc.
GPIO Interrupt Status Register
IC Address = Page-0: 42(0x2A), C Address = 0xA02A
IC Address = Page-0: 43(0x2B), C Address = 0xA02B
Table 221. GPIO Interrupt Status Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
VALUE
DESCRIPTION / COMMENTS
0
RESERVED
0b
R/W
RESERVED
[10:1]
GPIO_INT_STATUS 0000000000b RW1C 0 = No interrupt
1 = Interrupt
Event is defined by GPIO_IN_EDGE register
[15:11] RESERVED
R/W
RESERVED
GPIO Output Mode Register
IC Address = Page-0: 44(0x2C), C Address = 0xA02C
IC Address = Page-0: 45(0x2D), C Address = 0xA02D
Table 222. GPIO Output Mode Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
VALUE
DESCRIPTION / COMMENTS
0
RESERVED
0b
R/W
RESERVED
[10:1]
GPIO_OUT_MODE 1111111111b R/W
0 = CMOS output
1 = Open drain output
Sets the output mode for each corresponding
GPIO, GPIO1, GPIO2, GPIO3 and GPIO5 only
have open drain output mode.
[15:11] RESERVED
R/W
RESERVED
GPIO Off Register
IC Address = Page-0: 46(0x2E), C Address = 0xA02E
IC Address = Page-0: 47(0x2F), C Address = 0xA02F
Table 223. GPIO Off Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
VALUE
DESCRIPTION / COMMENTS
0
RESERVED 0b
R/W
RESERVED
[10:1]
GPIO_OFF
1111100000b R/W
0 = GPIO on
1 = GPIO off
Each bit shuts off the corresponding GPIO allowing the
external pin to be used for the TSC or ADC functions.
[15:11] RESERVED
R/W
RESERVED
相關(guān)PDF資料
PDF描述
P95020ZNQGI8 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
P95020ZLLG 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
P95020ZLLGI 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
P95020ZNQGI 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
P95020ZNQG 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
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