參數(shù)資料
型號： P95020NQG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù)： 23/169頁
文件大?。?/td> 4297K
代理商： P95020NQG8
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
119
2011 Integrated Device Technology, Inc.
General Purpose ADC Mode
In this mode, GPIO6/7/8/9 are analog general purpose
auxiliary signal inputs ADC1/ADC3/ADC2/ADC0. There
are also four other internal signals connect to the ADC
input multiplexer: BAT, TEMP, VSYS and ICHRG. These
signals are for battery voltage, die temperature, system
voltage and charging current measurement. To achieve
data coherency when result registers are read, use the I2C
burst mode to read the entire result.
ADC Auto Power Down Mode
In this mode, the ADC and internal reference are usually
off. When a measurement is either scheduled by the
internal timer or an external request, the device powers up
the ADC and internal reference, and then waits for the
internal reference to settle. After settling, the signal
acquisition starts. The ADC and the reference will be
powered
down
after
all
the
outstanding
scheduled/requested tasks are finished. All the
measurement channels are accessed in a round-robin
manner.
ADC Always On Mode
In this mode, the ADC is always powered up and the
internal ADC reference is always on. The internal
reference remains fully powered after completing a
sequence. All the measurement channels are accessed in
a round-robin manner.
System Monitoring and Alert Generation
There are four internal channels that support scheduled
measurement and monitoring:
-
Battery voltage (VBAT) measurement
-
Die Temperature (VTEMP) measurement
-
Vsys Level (VSYS) measurement
-
Battery charging current (CHRG_ICHRG)
measurement
Among those, three of them include alert signal generation:
-
Battery voltage
-
Die temperature
-
Vsys level
Measured results are saved in dedicated result registers
and compared with pre-defined spec limits. If the result is
out of the limit, an alert (map to processor interrupt) signal
can be asserted and alert status will be set.
ADC and TSC Module – Registers
PCON Register- ADC_TSC Enable Register
IC Address = Page-0: 39(0x39), C Address = 0xA039
Table 180. PCON Register- ADC_TSC Enable Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
VALUE
DESCRIPTION / COMMENTS
0
ADC_TSC_EN 0b
RW
0 = Disabled
1 = Enabled
Enable ADC or Touch screen controller. When disabled,
the ADC_TSC module retains the configuration register
settings but the clock is gated (low power mode).
[7:1] RESERVED
0000000b
RW
RESERVED
相關(guān)PDF資料
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