參數(shù)資料
型號： P95020NQG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù)： 140/169頁
文件大小： 4297K
代理商： P95020NQG8
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
72
2011 Integrated Device Technology, Inc.
Clock Generator – Pin Definitions
Table 108. Clock Generator Pin Definitions
PIN #
PIN_ID
DESCRIPTION
B20
32KHZ_OUT2
Buffered 32.768 kHz Output #2
A25
CKGEN_GND
PLL Analog Ground
B21
32KHZ_CLKIN/XTALIN
32KHZ_CLKIN: External 32.768 kHz clock input
XTALIN : Input pin when used with an external crystal
A26
XTALOUT/32KHZ_OUT1 XTALOUT: Output pin when used with an external crystal
32KHZ_OUT1: When XTALIN is connected to a 32 kHz input this pin can be a 32 kHz output
when bit 4 of the CKGEN_PLL_STATUS register is set to 1.
B22
VDD_CKGEN18
Internal 1.8V CKGEN LDO. Connect filter capacitor from this pin to CKGEN_GND
A27
HXTALOUT/TCXO_IN
HXTALOUT: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz Crystal oscillator output
TCXO_IN: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz TXCO Clock Input
B23
VDD_CKGEN33
Internal 3.3V CKGEN LDO. Connect filter capacitor from this pin to CKGEN_GND
A28
HXTALIN/TCXO_OUT1
HXTALIN: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz Crystal Oscillator Input
TCXO_OUT1: Buffered TXCO_IN/HXTAL Clock Output #1, 32.768 kHz Output, 24 MHz PLL
Output
B24
TCXO_OUT2
Buffered TXCO_IN/HXTAL Clock Output #2, 12 MHz PLL Output, 48 MHz PLL Output
A29
SYS_CLKOUT
12 MHz Output or Buffered Output of TCXO_IN/HXTAL
B25
CKGEN_GND
PLL Analog Ground
A30
USB_CLKOUT
24 MHz or 48 MHz Output
B26
VDDIO_CK
Power Supply Input for TCXO_OUT1 and TCXO_OUT2 (1.1V – 1.9V)
Clock Generator – Oscillator Electrical Characteristics
Unless otherwise specified, typical values at TA = 25°C, VDD_CKGEN33 = 3.3V, VDD_CKGEN18 = 1.8V, VSYS = 3.8V,
TA = 0°C to +70°C.
Table 109. Clock Oscillator Circuit Electrical Specifications
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VDD_CKGEN33
Operating Voltage
Internal LDO Regulator
2.97
3.3
3.63
V
VDD_CKGEN18
Internal LDO Regulator
1.62
1.8
1.98
V
VDDIO_CK
Power Input for
TCXO_OUT1 and
TCXO_OUT2
1.1
1.9
V
IDD_CKGEN33
Supply Current
4
mA
IDD_CKGEN18
1
mA
VDDIO_CK
2
mA
VIH
TCXO_IN High Level Input Voltage
0.7xVDD_
CKGEN18
VDD_CKG
EN18 + 0.3
V
VIL
TCXO_IN Low Level Input Voltage
-0.3
0.3xVDD_C
KGEN18
V
VIH
32KHZ_CLKIN High Level Input Voltage
0.7x VLD0_LP
VLD0_LP +
0.3
V
VIL
32KHZ_CLKIN Low Level Input Voltage
-0.3
0.3x VLD0_LP
V
VOH
Output High for SYS_CLK, USB_CLK
IOH = -4mA
0.7xVDD_
CKGEN33
V
VOL
Output Low for SYS_CLK, USB_CLK
IOL = 4mA
0.3xVDD_C
KGEN33
V
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