參數(shù)資料
型號： P95020NQG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù)： 156/169頁
文件大?。?/td> 4297K
代理商： P95020NQG8
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
87
2011 Integrated Device Technology, Inc.
General Purpose Time Count Register
IC Address = Page-0: 163(0xA3), C Address = 0xA0A3
Table 140. General Purpose Time Count Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
VALUE
DESCRIPTION / COMMENTS
[7:0] GPTIME
FFh
R/W
User programmed number of cycles to timeout General Purpose Timer Count
Watchdog Timer Count Register
IC Address = Page-0: 164(0xA4), C Address = 0xA0A4
Table 141. Watchdog Timer Count Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
VALUE
DESCRIPTION / COMMENTS
[7:0] WDTIME
FFh
R/W
User programmed number of cycles to timeout Watchdog Timer Count
General Purpose Timer Timebase Register
IC Address = Page-0: 165(0xA5), C Address = 0xA0A5
Table 142. General Purpose Timer Timebase Register
BIT
BIT NAME
DEFAULT SETTING
USER TYPE VALUE
DESCRIPTION / COMMENTS
[1:0] GPTB
00b
R/W
00: 32.768 kHz
01: 1024 Hz
10: 1 Hz
11: 1 Minute
General Purpose Timer Timebase
[3:2] RESERVED
R/W
RESERVED
[5:4] WDTB
00b
R/W
00: 8 Hz
01: 1 Hz
10: 0.5 Hz
11: 1 Minute
Watchdog Timer Timebase
[7:6] RESERVED
R/W
RESERVED
Timer Interrupt Enable Register
IC Address = Page-0: 166(0xA6), C Address = 0xA0A6
Table 143. Timer Interrupt Enable Register
BIT
BIT NAME
DEFAULT SETTING
USER TYPE VALUE
DESCRIPTION / COMMENTS
0
GPT_INTEN
0b
R/W
1: Enabled
0: Disabled
General Purpose Timer Interrupt Enable
[3:1]
RESERVED
000b
R/W
RESERVED
4
WDT_INTEN
0b
R/W
1: Enabled
0: Disabled
Watchdog Timer Interrupt Enable
[7:5]
RESERVED
000b
R/W
RESERVED
Reserved Registers
These registers are reserved. Do not write to them.
IC Address = Page-0: 167(0xA7), C Address = 0xA0A7
Thru = Page-0: 175(0xAF), C Address = 0Xa0AF
相關(guān)PDF資料
PDF描述
P95020ZNQGI8 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
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