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參數(shù)資料
| 型號： | P95020NQG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | 10 X 10 MM, 0.85 MM HEIGHT, QFN-132 |
| 文件頁數(shù)： | 50/169頁 |
| 文件大?。?/td> | 4297K |
| 代理商： | P95020NQG8 |
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IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
143
2011 Integrated Device Technology, Inc.
IC Slave
IC Slave Address and Timing Mode
The IC ports on the IDTP95020 operate at a maximum
speed of 400 kHz. The IC slave address that the
IDTP95020
responds
to
is
defined
in
the
I2C_SLAVE_ADDR global register. The default IC device
address after reset is 0101010, and can be changed by
firmware during the start up sequence.
The IC slave supports two interface timing modes: Non-
Stretching and Stretching.
In Non-Stretching Mode, the IC slave does not stretch the
input clock signal. The registers are pre-fetched to speed
up the read access in order to meet the 400 kHz speed.
This is the default mode of operation and is intended for
use with IC masters that do not supporting clock
stretching.
In Stretching Mode, the IC slave may stretch the clock
signal (hold I2CS_SCL low) during the ACK / NAK phase
(byte level stretching) when the internal read access
request is not finished. Stretching is not supported during
write accesses.
IC Slave Write/Read Operation
The configuration and status registers for the various
functional blocks are mapped to 3 consecutive 256 byte
pages. The page ID is encoded to 0,1, and 2. The
definition and mapping is defined in Table 11 – Register
Address Global Mapping on Page 16. The first 16 bytes in
any of the 3 pages map to the same set of global registers.
The “current active page” ID for IC access is defined in
the global page ID register.
The IC uses an 8-bit register address (Reg_addr in
Figure 47 below) to define the register access start
address in an IC access in the current page. The register
address can be programmed by writing the register value
immediately after device address.
Subsequent write
accesses will be directed to the register defined by the
register address in the current active page.
Read
accesses will return the register defined by the register
address.
The register address is incremented
automatically byte-per-byte during each read/write access.
Figure 47. I2C Read / Write Operation
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PDF描述 |
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| P95020ZNQGI8 | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| P95020ZLLG | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
| P95020ZLLGI | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
| P95020ZNQGI | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| P95020ZNQG | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P95020ZDLLG | 制造商:Integrated Device Technology Inc 功能描述:124-LGA - Bulk |
| P95020ZDLLG8 | 制造商:Integrated Device Technology Inc 功能描述:124-LGA - Tape and Reel |
| P95020ZDNQG | 制造商:Integrated Device Technology Inc 功能描述:132-VFQFPN - Bulk |
| P95020ZDNQG8 | 制造商:Integrated Device Technology Inc 功能描述:132-VFQFPN - Tape and Reel |
| P95021NQG | 功能描述:PMIC 解決方案 Integrates Audio, LED B/Light Pwr Mgt RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
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