參數(shù)資料
型號： P95020NQG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù)： 111/169頁
文件大?。?/td> 4297K
代理商： P95020NQG8
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
46
2011 Integrated Device Technology, Inc.
ADC1 Digital Boost Gain Control Register
This register selects the amount of boost applied after ADC1 but before the ADC1 output gain/AGC.
ADC1_IN_DBOOST: IC Address = Page-1: 182(0xB6), C Address = 0xA1B6, Offset = 0xB6
Table 64. ADC1 Digital Boost Gain Control Register
BIT
BIT NAME
DEFAULT SETTING USER TYPE VALUE
DESCRIPTION / COMMENTS
[1:0] DBR
11b
RW
0h = 30 dB Gain
1h = 20 dB Gain
2h = 10 dB Gain
3h = 0 dB Gain
Right Boost
[3:2] RESERVED 00b
RW
RESERVED
[5:4] DBL
11b
RW
0h = 30 dB Gain
1h = 20 dB Gain
2h = 10 dB Gain
3h = 0 dB Gain
Left Boost
[7:6] RESERVED 00b
RW
RESERVED
ADC1 Control Register
This register controls the function of the High pass filter for ADC1
ADC1_CTRL: IC Address = Page-1: 183(0xB7), C Address = 0xA1B7, Offset = 0xB7
Table 65. ADC1 Control Register
BIT
BIT NAME
DEFAULT SETTING USER TYPE VALUE
DESCRIPTION / COMMENTS
[3:0] RESERVED 0000b
RW
RESERVED
4
HPF_FREZ
0b
RW
0 = Disabled
1 = Enabled
High-pass filter freeze
5
RESERVED 0b
RW
RESERVED
6
HPF_DIS
0b
RW
0 = Not Disabled
1 = Disabled
High Pass Filter Disable
7
RESERVED 0b
RW
RESERVED
Microphone Port Mode Control
Microphone mode selection and other microphone port
related control.
The digital and analog port pins are shared. Analog or
digital microphone mode is selected using this register.
When in digital mode, the DMICCLK, DMICDAT1,
DMICDAT2 and DMICCSEL functions are available.
When in analog mode, the MIC_R+, MIC_R-, MIC_L+,
MIC_L-, MICBIAS_R, MICBIAS_L are available.
The left and right outputs of ADC1 may be swapped using
the L/R swap flag and mono output may be forced using
the mono flag. By using the L/R swap and mono flags
together it is possible to support stereo capture, mono
capture from the left channel and mono capture from the
right channel. When used in conjunction with the power
management controls, it is possible to shut down half of
the ADC and still provide valid data on both the left and
right digital output streams from ADC1.
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