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參數(shù)資料
| 型號(hào)： | P95020NQG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | 10 X 10 MM, 0.85 MM HEIGHT, QFN-132 |
| 文件頁數(shù)： | 74/169頁 |
| 文件大?。?/td> | 4297K |
| 代理商： | P95020NQG8 |
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IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
165
2011 Integrated Device Technology, Inc.
APPLICATIONS INFORMATION
External Components
The IDTP95020 requires a minimum number of external
components for proper operation.
Digital Logic Decoupling Capacitors
As with any high-performance mixed-signal IC, the
IDTP95020 must be isolated from the system power
supply noise to perform optimally. A decoupling capacitor
of 0.01μF must be connected between each power supply
and the PCB ground plane as close to these pins as
possible.
For optimum device performance, the
decoupling capacitor should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Class D Considerations
The CLASS_D amplifier should have one 330uF and one
0.1uF capacitor to ground at its VDD pin.
The CLASS_D output also should have a series
connected snubber consisting of a 3.3, 0603 resistor and
a 680pF capacitor across the speaker output pins. No
other filtering is required.
The CLASS_D BTL plus and minus output traces must be
routed side by side in pairs.
Series Termination Resistors
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a commonly
used trace impedance), place a 33 resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20.
IC External Resistor Connection
The SCL and SDA pins can be connected to any voltage
between 1.71V and 3.6V.
Crystal Load Capacitors
To save discrete component cost, the IDTP95020
integrates on-chip capacitance to support a crystal with
CL=10pF. It is important to keep stray capacitance to a
minimum by using very short PCB traces between the
crystal and device. Avoid the use of vias if possible.
Buck and Boost Converters
-
The input capacitors (CIN) should be connected
directly between the power VIN and power GND pins.
-
The output capacitor (COUT) and power ground should
be connected together to minimize any DC regulation
errors caused by ground potential differences.
-
The output-sense connection to the feedback pins
should be separated from any power trace. Route the
output-sense trace as close as possible to the load
point to avoid additional load regulation errors.
Sensing along a high-current load trace will degrade
DC load regulation.
-
The power traces, including GND traces, the SW or
OUT traces and the VIN trace should be kept short,
direct and wide to allow large current flow. The
inductor connection to the SW or OUT pins should be
as short as possible. Use several via pads when
routing between layers.
PCB Layout Considerations
-
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed. Please contact IDT Inc. for gerber files that
contain the recommended board layout.
-
As for all switching power supplies, especially those
providing high current and using high switching
frequencies, layout is an important design step. If
layout is not carefully done, the regulator could show
instability as well as EMI problems. Therefore, use
wide and short traces for high current paths.
-
The 0.01μF decoupling capacitors should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins.
The PCB trace to each VDD pin should be kept as
short as possible, as should the PCB trace to the
ground via.
-
The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
-
To minimize EMI, the 33 series termination resistor
(if needed) should be placed close to the clock output.
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