參數(shù)資料
型號: P95020NQG8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 電源管理
英文描述: 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝: 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù): 164/169頁
文件大?。?/td> 4297K
代理商: P95020NQG8
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
94
2011 Integrated Device Technology, Inc.
Buck Regulators – Control Register
(See Table 145 for addresses: 0xA081, 0xA083 and 0xA085)
The Control Register contains the Current Limit setting bits[3:2], Control bits[1:0] and Status bits[5:4].
Table 148. Buck Regulators Control Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
VALUE
DESCRIPTION / COMMENTS
0
PWM_PFM
0
RW
1 = PFM mode
0 = PWM mode
PWM/PFM Mode Select
1
CLK_SEL
1
RW
1 = 2 MHz
0 = 1 MHz
Clock Frequency
[3:2] I_LIM
3h
RW
(See Table 149)
Cycle by Cycle Current Limit (%)
4
SC_FAULT
N/A
R
1 = Fault
0 = OK
Short Circuit Fault
5
PGOOD
N/A
R
1 = Power Good
0 = Power Not Good
Power Good
6
RESERVED
1b
RW
RESERVED
7
DAC_MSB_EN 1b
RW
1 = Enable writes to BUCK 3 MSB bits in DAC
0 = Disable writes to BUCK 3 MSB bits in DAC
BUCK VOUT 3 MSB bits write
protection
Table 149. Control Register Cycle by Cycle Current Limit (I_LIM) Settings for Bits [3:2]
BIT 3
BIT 2
DESCRIPTION
0
Current Limit = 25 %
0
1
Current Limit = 50 %
1
0
Current Limit = 75 %
1
Current Limit = 100 % [Note]above
Note: Current Limit is at maximum when bits [3:2] are both set to 1.
Table 150. Buck Regulators Control Register Setting for different Operating Mode
DESCRIPTION
ADDRESS (I2C)
VALUE
Not Operating
Page-x: 05(0x05)[2:0] Global enable for
Buck#2, Buck#1 and Buck#0
0x05 [0] = 0
0x05 [1] = 0
0x05 [2] = 0
Operating PFM Mode
Page-0:129( 0x81[0]) for
Buck#0 (500mA)
Page-0: 131(0x83[0]) for
Buck#1 (500mA)
Page-0: 131(0x85[0]) for
Buck#2 (1000mA)
0x81 [0] = 1
0x83 [0] = 1
0x85 [0] = 1
Operating PWM Mode
Page-0: 129(0x81[0]) for
Buck#0 (500mA)
Page-0: 131(0x83[0]) for
Buck#1 (500mA)
Page-0: 133(0x85[0]) for
Buck#2 (1000mA)
0x81 [0] = 0
0x83 [0] = 0
0x85 [0] = 0
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