參數(shù)資料
型號： P95020NQG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù)： 101/169頁
文件大小： 4297K
代理商： P95020NQG8
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
37
2011 Integrated Device Technology, Inc.
Class D – EQREAD_DATA Registers
This 24-bit register serves as the 24-bit data holding register used when doing indirect reads to the EQRAM.
IC Address = Page-2: 54(0x36), C Address = 0xA236
IC Address = Page-2: 55(0x37), C Address = 0xA237
IC Address = Page-2: 56(0x38), C Address = 0xA238
Table 38. Class D – EQREAD_DATA Registers
BIT
BIT NAME
DEFAULT SETTING USER TYPE VALUE
DESCRIPTION / COMMENTS
[23:0] EQREAD_DATA 000000h
R
24 bit coefficient 24-bit data register to read data on EQRAM
Class D – EQWRITE_DATA Registers
This 24-bit register serves as the 24-bit data holding registers when doing indirect writes to the EQRAM.
IC Address = Page-2: 57(0x39), C Address = 0xA239
IC Address = Page-2: 58(0x3A), C Address = 0xA23A
IC Address = Page-2: 59(0x3B), C Address = 0xA23B
Table 39. Class D – EQWRITE_DATA Registers
BIT
BIT NAME
DESCRIPTION / COMMENTS
[23:0] EQWRITE_DATA 000000h
RW
24 bit coefficient 24-bit data register to write data on EQRAM
Class D – EQ_ADDR Registers
This 16-bit register provides the 10-bit address to the internal RAM when performing indirect writes/reads to the EQRAM.
EQ_ADDR_HI: IC Addresses = Page-2: 60(0x3C), C Address = 0xA23C
EQ_ADDR_LO: IC Addresses = Page-2: 61(0x3D), C Address = 0xA23D
Table 40. Class D – EQ_ADDR Registers
BIT
BIT NAME
DEFAULT SETTING
USER TYPE
VALUE
DESCRIPTION / COMMENTS
[9:0]
EQ_ADDR
0000000000b
RW
10-bit Address EQRAM is mapped on address space 0 to 51.
[15:10] RESERVED 000000b
RW
RESERVED
Class D – EQCONTROL HI and LO Register
This 16-bit register provides the write/read enable when doing indirect writes/reads to the EQRAM.
IC Address = Page-2: 62(0x3E), C Address = 0xA23E
IC Address = Page-2: 63(0x3F), C Address = 0xA23F
Table 41. Class D – EQCONTROL HI and LO Register
BIT
BIT NAME
DEFAULT SETTINGS USER TYPE VALUE
DESCRIPTION / COMMENTS
[13:0] RESERVED 0000000000000b
RW
RESERVED
14
eqram_rd
0b
RW1C
0 = Don’t Read
1 = Read
Read from EQRAM, cleared by HW when done
15
eqram_wr
0b
RW1C
0 = Don’t Write
1 = Write
Write to EQRAM, cleared by HW when done
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