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9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
99 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
initialization of the Peripheral Controller. If DMA is not required by the application,
DMACLKON can be permanently disabled to save current. The burst counter, DMA bus
width, and the polarity of DC_DREQ and DC_DACK must be accordingly set.
The ISP1761 supports only the counter mode DMA transfer. To enable the counter mode,
ensure that DIS_XFER_CNT in the DcDMAConfiguration register (address: 0238h) is set
to zero. Set bit EOT_POL in the DMA Hardware register (address: 023Ch) to logic 1, to
make the EOT function invalid because the ISP1761 does not support the external EOT
mode.
Before starting the DMA transfer, preset the interrupt enable bit IEDMA in the Interrupt
Enable register (address: 0214h) and the DMA Interrupt Enable register (address: 0254h).
The ISP1761 supports two interrupt trigger modes: level and edge. The pulse width, which
in an edge mode, is determined by setting the Interrupt Pulse Width register (address:
0280h). The default value is 1Eh, which indicates that the interrupt pulse width is 1
μ
s.
The minimum interrupt pulse width is approximately 30 ns when set to logic 1. Do not
write a zero to this register.
The interrupt polarity also must be correctly set.
Remark:
DMA can apply to all endpoints on the chip. It, however, can only take place for
one endpoint at a time. The selected endpoint is assigned by setting the endpoint number
in the DMA Endpoint register (address: 0258h). It will also internally redirect the endpoint
buffer of the selected endpoint to the DMA controller bus. In addition, it requires a
preceding process to program the endpoint type, the endpoint maximum packet size, and
the direction of the endpoint.
When setting the Endpoint Index register (address: 022Ch), the endpoint buffer of the
selected endpoint is directed to the internal CPU bus for the PIO access. Therefore, it is
required to reconfigure the Endpoint Index register with endpoint number, which is not an
endpoint number in use for the DMA transfer to avoid any confusion.
10.1.1.4
Starting DMA
Dynamically assign the DMA Transfer Counter register (address: 0234h) for each DMA
transfer.
The transfer will end once transfer counter reaches zero. Bit DMA_XFER_OK in the DMA
Interrupt Reason register (address: 0250h) will be asserted to indicate that the DMA
transfer has successfully stopped. If the transfer counter is larger than the burst counter,
the DC_DREQ signal will drop at the end of each burst transfer. DC_DREQ will reassert at
the beginning of each burst. For a 32-bit DMA transfer, the minimum burst length is 4 B.
This means that the burst length is only one DMA cycle. Therefore, DC_DREQ and
DC_DACK will toggle by each DMA cycle. For a 16-bit DMA transfer, the minimum burst
length is 2 B.
Setting bit GDMA read or GDMA write in the DMA Command register (address: 0230h)
will start the DMA transfer.
10.1.1.5
DMA stop and interrupt handling
The DMA transfer will either successfully complete or terminate, which can be identified
by reading the status in the DcInterrupt register (address: 0218h) and DMA Interrupt
Reason register (address: 0250h) while in the Interrupt Service Routine.