參數(shù)資料
型號: ISP1761BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 56/158頁
文件大小: 724K
代理商: ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
56 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
8.4.3
ISO IRQ MASK OR register (R/W: 0318h)
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
Table 57
for bit description. For details,
see
Section 7.4
.
8.4.4
INT IRQ MASK OR register (R/W: 031Ch)
Each bit of this register (see
Table 58
) corresponds to one of the 32 INT PTDs defined,
and is a hardware IRQ mask for each PTD done map. For details, see
Section 7.4
.
8.4.5
ATL IRQ MASK OR register (R/W: 0320h)
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
Table 59
for bit description. For details,
see
Section 7.4
.
8.4.6
ISO IRQ MASK AND register (R/W: 0324h)
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Section 7.4
.
Table 60
provides the bit description of the register.
Table 57:
Bit
31 to 0
ISO IRQ MASK OR register: bit description
Symbol
Access Value
ISO_IRQ_
MASK_OR
[31:0]
Description
ISO IRQ Mask OR
: Represents a direct map for
ISO PTDs 31 to 0.
0 —
No OR condition defined between ISO PTDs
1 —
The bits corresponding to certain PTDs are set
to logic 1 to define a certain OR condition.
R/W
0000 0000h
Table 58:
Bit
31 to 0
INT IRQ MASK OR register: bit description
Symbol
Access
Value
INT_IRQ_
MASK_OR
[31:0]
Description
R/W
0000 0000h
INT IRQ Mask OR
: Represents a direct map for
INT PTDs 31 to 0.
0 —
No OR condition defined between INT PTDs
31 to 0
1 —
The bits corresponding to certain PTDs are set
to logic 1 to define a certain OR condition.
Table 59:
Bit
31 to 0
ATL IRQ MASK OR register: bit description
Symbol
Access
Value
ATL_IRQ_
MASK_OR
[31:0]
Description
R/W
0000 0000h
ATL IRQ Mask OR
: Represents a direct map for
ATL PTDs 31 to 0.
0 —
No OR condition defined between the ATL
PTDs
1 —
The bits corresponding to certain PTDs are set
to logic 1 to define a certain OR condition.
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