參數(shù)資料
型號: ISP1761BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 119/158頁
文件大小: 724K
代理商: ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
119 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.6.6
DMA Interrupt Enable register (R/W: 0254h)
This 2 B register controls the interrupt generation of the source bits in the DMA Interrupt
Reason register. The bit allocation is given in
Table 132
. The bit description is given in
Table 130
.
Logic 1 enables the interrupt generation. The values after a (bus) reset are logic 0
(disabled).
[1]
The reserved bits should always be written with the reset value.
Table 130: DMA Interrupt Reason register: bit description
Bit
Symbol
Description
15 to 13
-
reserved
12
GDMA_STOP
GDMA Stop
: When the GDMA_STOP command is issued to the
DMA Command registers, it means that the DMA transfer has
successfully terminated.
11
-
reserved
10
INT_EOT
Internal EOT
: Logic 1 indicates that an internal EOT is detected;
see
Table 131
.
9
-
reserved
8
DMA_XFER_OK
DMA Transfer OK
: Logic 1 indicates that the DMA transfer has
been completed (DMA Transfer Counter has become zero). This bit
is only used in the GDMA (slave) mode.
7 to 0
-
reserved
Table 131: Internal EOT-functional relation with the DMA_XFER_OK bit
INT_EOT
DMA_XFER_OK
Description
1
0
During the DMA transfer, there is a premature termination with
short packet.
1
1
DMA transfer is completed with short packet and the DMA
transfer counter has reached 0.
0
1
DMA transfer is completed without any short packet and the
DMA transfer counter has reached 0.
Table 132: DMA Interrupt Enable register: bit allocation
Bit
15
Symbol
reserved
[1]
14
13
12
11
10
9
8
IE_GDMA_
STOP
0
0
R/W
4
reserved
[1]
IE_INT_
EOT
0
0
R/W
2
reserved
[1]
IE_DMA_
XFER_OK
0
0
R/W
0
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
0
0
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
1
reserved
[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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