參數資料
型號: ISP1761BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數: 49/158頁
文件大?。?/td> 724K
代理商: ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
49 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
8.3.10
DMA Start Address register (W: 0344h)
This register defines the start address select for the DMA read and write operations. See
Table 49
for bit allocation.
[1]
The reserved bits should always be written with the reset value.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
15
14
13
12
11
10
9
8
NO_OF_CLK[15:8]
0
R/W
4
NO_OF_CLK[7:0]
0
R/W
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 48:
Bit
31 to 24
Edge Interrupt Count register: bit description
Symbol
Description
MIN_
WIDTH[7:0]
interrupts in
μ
SOFs (1
μ
SOF = 125
μ
s). This is not valid for level
interrupts. A count of zero means that interrupts occur as and when an
event occurs.
-
reserved
NO_OF_
CLK[15:0]
must be kept asserted on the interface.16 clocks of 60 MHz on POR if
this register has a value of 0000h. The default IRQ pulse width is
approximately 500 ns.
Minimum Width
: Indicates the minimum width between two edge
23 to 16
15 to 0
Number of Clocks
: Count in number of clocks that the edge interrupt
Table 49:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DMA Start Address register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
W
23
0
W
22
0
W
21
0
W
20
0
W
19
0
W
18
0
W
17
0
W
16
reserved
[1]
0
W
15
0
W
14
0
W
13
0
W
12
0
W
11
0
W
10
0
W
9
0
W
8
START_ADDR_DMA[15:8]
0
W
4
START_ADDR_DMA[7:0]
0
W
0
W
7
0
W
6
0
W
5
0
W
3
0
W
2
0
W
1
0
W
0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
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