參數(shù)資料
型號： ISP1761BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 120/158頁
文件大?。?/td> 724K
代理商： ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
120 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.6.7
DMA Endpoint register (R/W: 0258h)
This 1 B register selects a USB endpoint FIFO as the source or destination for DMA
transfers. The bit allocation is given in
Table 133
.
[1]
The reserved bits should always be written with the reset value.
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (022Ch) at any time. Doing so would result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the
DMA Endpoint register, however, is pointed to an active endpoint, the firmware must not
reference the same endpoint on the Endpoint Index register.
10.6.8
DMA Burst Counter register (R/W: 0264h)
The bit allocation of the register is given in
Table 135
.
[1]
The reserved bits should always be written with the reset value.
Table 133: DMA Endpoint register: bit allocation
Bit
7
Symbol
Reset
0
Bus reset
0
Access
R/W
6
5
4
3
2
1
0
reserved
[1]
EPIDX[2:0]
0
0
R/W
DMADIR
0
0
R/W
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Table 134: DMA Endpoint register: bit description
Bit
Symbol
7 to 4
-
3 to 1
EPIDX[2:0]
0
DMADIR
Description
reserved
Selects the indicated endpoint for DMA access
DMA Direction
:
0 —
Selects the RX/OUT FIFO for DMA read transfers
1 —
Selects the TX/IN FIFO for DMA write transfers.
Table 135: DMA Burst Counter register: bit allocation
Bit
15
Symbol
Reset
0
Bus reset
0
Access
R/W
Bit
7
Symbol
Reset
0
Bus reset
0
Access
R/W
14
13
12
11
10
9
8
reserved
[1]
0
0
R/W
6
BURSTCOUNTER[12:8]
0
0
R/W
R/W
3
0
0
0
0
0
0
0
0
0
0
R/W
5
R/W
4
R/W
1
R/W
0
2
BURSTCOUNTER[7:0]
0
0
R/W
0
0
0
0
0
0
0
0
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
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