參數(shù)資料
型號: ISP1761BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 101/158頁
文件大?。?/td> 724K
代理商: ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
101 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.3 Differences between the ISP1761 and ISP1582 Peripheral Controller
This section explains the variations between the ISP1761 and ISP1582 Peripheral
Controller in terms of register bits and their associated functions.
10.3.1
ISP1761 initialization registers
The ISP1582 supports the 16-bit bus access. The register addresses are 2 B aligned.
The ISP1761 supports the 16-bit and 32-bits bus accesses. To support the 32-bit
access, the DATA_BUS_WIDTH bit in the HW Mode Control register must be
initialized.
In 32-bit bus access mode, the register addresses are 4 B aligned. Therefore, the
DcBufferStatus register can be accessed using the upper-two bytes of the Buffer
Length register.
The SOFTCT bit in the Mode register has been removed. The DP_PULLUP control bit
in the OTG Control register is used in the ISP1761 in place of the SOFTCT bit in the
ISP1582.
Added the Interrupt Pulse Width register to define the pulse width of the interrupt
signal.
10.3.2
ISP1761 DMA
The DACK-only mode has been removed. It only supports the counter mode.
The external-EOT mode has been removed. There is no EOT pin on the chip.
Supports the 16-bit and 32-bit DMA. Does not support the 8-bit DMA.
The RD_N and WR_N signals are available for the DMA data strobe. These signals
are also used as data strobe signals during the PIO access. An internal multiplex will
redirect these signals to the DMA controller for the DMA transfer or to registers for the
PIO access.
For details on the DMA programming, refer to application note ISP1761 Peripheral DMA
Initialization (AN10040)
10.3.3
ISP1761 peripheral suspend indication
A HIGH level indicates that the peripheral has entered suspend mode. The pulse
indication mode has been removed.
10.3.4
ISP1761 interrupt and DMA common mode
In the common mode, the interrupt and DMA signals of the Peripheral Controller are
redirected to pins that are used by the Host Controller because the Host Controller and
the Peripheral Controller share the same pins. Some control bits must be set in the HW
Mode Control register, see
Section 8.3.1
.
EP6TX
EP7RX
EP7TX
Programmable
Programmable
Programmable
Yes
Yes
Yes
Programmable
Programmable
Programmable
OUT
IN
OUT
Table 92:
Endpoint
identifier
Endpoint access and programmability
…continued
Maximum packet
size
Double buffering Endpoint type
Direction
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ISP1761BE,551 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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