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參數(shù)資料
| 型號(hào)： | ISP1761BE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Hi-Speed Universal Serial Bus On-The-Go controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128 |
| 文件頁(yè)數(shù)： | 58/158頁(yè) |
| 文件大?。?/td> | 724K |
| 代理商： | ISP1761BE |
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9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
58 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
EHCI manages schedules in two lists: periodic and asynchronous. The data structures
are designed to provide the maximum flexibility required by USB, minimize memory traffic,
and hardware and software complexity. The ISP1761 controller executes transactions for
devices by using a simple shared-memory schedule. This schedule consists of data
structures organized into three lists:
qISO —
Isochronous transfer
qINTL —
Interrupt transfer
qATL —
Asynchronous transfer; for the control and bulk transfers.
The system software maintains two lists for the Host Controller: periodic and
asynchronous. The root of the periodic schedule—the PERIODICLISTBASE register—is
the physical memory base address of the periodic frame list. The periodic frame list is an
array memory pointer. The objects referenced from the frame list must be valid schedule
data structures. The asynchronous list base is also a common list of queue heads
(endpoints) that are served in a schedule. These endpoint data structures are further
linked to the EHCI transfer descriptor that is the valid schedule (queue PTD).
The Periodic Schedule Enable (ISO_BUF_FULL and INT_BUF_FULL) or Asynchronous
Schedule Enable (ATL_BUF_FULL) bits can enable traversal to these lists. Enabling a list
indicates the presence of valid schedule in the list. The system software starts at these
points, schedules the first transfer inside the shared memory of the ISP1761, and sets up
the ATL, INTL or ITL bit corresponding to the type of transfer scheduled in the shared
memory.
The ISP1761 has a maximum of 32 ISO, 32 INTL and 32 ATL PTDs. These PTDs are
used as channels to transfer data from the shared memory to the USB bus. These
channels are allocated and deallocated on receiving the transfer from the core USB driver.
Multiple transfers are scheduled to the shared memory for various endpoints by traversing
the next link pointer provided by the EHCI data structure, until it reaches the terminate bit
in a microframe. If a schedule is enabled, the Host Controller starts executing from the
ISO schedule, before it goes to the INTL schedule, and then to the ATL schedule.
The EHCI periodic and asynchronous lists are traversed by the software according to the
EHCI traversal rule, and executed only from the asynchronous schedule after it
encounters the end of the periodic schedule. The Host Controller traverses the ISO, INTL
and ATL schedules. It fetches the element and begins traversing the graph of linked
schedule data structures.
The last bit identifies the end of the schedule for each type of transfer, indicating the rest
of the channels are empty. Once a transition is completed, the Host Controller executes
from the next transfer descriptor in the schedule until the end of the microframe.
The completion of a transfer is indicated to the software by the interrupt that can be
grouped over the various PTDs by using the AND or OR registers that are available for
each schedule type (ISO, INTL and ATL). These registers are simple logic registers to
decide the group and individual PTDs that can interrupt the CPU for a schedule, when the
logical conditions of the done bit is true in the shared memory that completes the interrupt.
Interrupts are of four types and the latency can be programmed in multiples of
μ
SOF
(125
μ
s):
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1761ET | Hi-Speed Universal Serial Bus On-The-Go controller |
| ISP2100A | Telecommunication IC |
| ISP2100BN4 | Microprocessor |
| ISP2300 | Controller Miscellaneous - Datasheet Reference |
| ISP2310 | Controller Miscellaneous - Datasheet Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1761BE,518 | 功能描述:USB 接口集成電路 USB HS OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,557 | 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE518 | 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB OTG 128LQFP |
| ISP1761BEGE | 功能描述:IC USB CTRL HI-SPEED 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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