參數(shù)資料
型號(hào): ISP1761BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 76/158頁
文件大?。?/td> 724K
代理商: ISP1761BE
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8.5.5
Start and complete split for isochronous, SiTD
Table 71
shows the bit allocation for start and complete split for isochronous, Split isochronous Transfer Descriptor (SiTD)
5
.
9
P
R
7
P
I
H
[1]
Reserved.
[2]
Note the change in the position of USCS[7:0] and NrBytesReceived_CS_IN.
[3]
EndPt[0].
5.
Patent-pending: Start and complete split for isochronous, SiTD.
Table 71:
Bit
DW7
DW5
DW3
Start and complete split for isochronous, SiTD: bit allocation
62
61
60
59
58
57
56
63
55
54
53
52
reserved
ISO_IN_1[7:0]
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
ISO_IN_7[7:0]
μ
SCS[7:0]
[2]
ISO_IN_2[7:0]
B
X
ISO_IN_0[7:0]
A
H
S
C
[1]
D
T
reserved
NrBytesTransferred[11:0]
DW1
HubAddress[6:0]
PortNumber[6:0]
reserved
S
EP
Type
[1:0]
13
ISO_IN_4[7:0]
Status1
[2:0]
Token
[1:0]
DeviceAddress[6:0]
EndPt[3:0]
(31 to 34)
Bit
DW6
DW4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
12
11
10
9
8
7
6
5
4
3
2
1
0
ISO_IN_6[7:0]
Status6
ISO_IN_5[7:0]
Status4
[2:0]
ISO_IN_3[7:0]
μ
SA[7:0]
Status7
[2:0]
[2:0]
Status5
[2:0]
Status3
[2:0]
Status2
[2:0]
Status0
[2:0]
DW2
DW0
reserved
DataStartAddress[15:0]
μ
Frame[7:0] (full-speed)
[3]
[1]
TT_MPS_Len[10:0]
NrBytesToTransfer[14:0] (1 kB for full-speed)
[1]
V
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