參數(shù)資料
型號: ISP1761BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 117/158頁
文件大小: 724K
代理商: ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
117 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
10.6.4
DMA Hardware register (R/W: 023Ch)
The DMA Hardware register consists of 1 B. The bit allocation is shown in
Table 127
.
This register determines the polarity of the bus control signals (DACK and DREQ). It also
controls whether the upper and lower parts of the data bus are swapped (bits
ENDIAN[1:0]) for the GDMA (slave) mode.
[1]
The reserved bits should always be written with the reset value.
Table 125: DcDMAConfiguration register: bit allocation
Bit
15
Symbol
Reset
0
Bus Reset
0
Access
R/W
Bit
7
Symbol
DIS_
XFER_CNT
Reset
0
Bus Reset
0
Access
R/W
14
13
12
11
10
9
8
reserved
[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
WIDTH
6
reserved
[1]
MODE[1:0]
reserved
0
0
0
0
0
0
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 126: DcDMAConfiguration register: bit description
Bit
Symbol
15 to 8
-
7
DIS_XFER_CNT
Description
reserved
Disable Transfer Counter
: Logic 1 disables the DMA Transfer
Counter (see
Table 123
).
reserved
Mode
: These bits only affect the GDMA slave handshake signals.
00 —
WR_N slave strobes data from the DMA bus into the
ISP1761; RD_N slave puts data from the ISP1761 on the DMA bus
01, 10, 11 —
reserved
reserved
Width
: This bit selects the DMA bus width for the GDMA slave.
0 —
32-bit data bus
1 —
16-bit data bus.
6 to 4
3 to 2
-
MODE[1:0]
1
0
-
WIDTH
Table 127: DMA Hardware register: bit allocation
Bit
7
Symbol
ENDIAN[1:0]
6
5
4
3
2
1
0
EOT_POL
reserved
[1]
DACK_
POL
0
0
R/W
DREQ_
POL
1
1
R/W
reserved
[1]
Reset
Bus reset
Access
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
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