參數(shù)資料
型號: ISP1761BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 70/158頁
文件大?。?/td> 724K
代理商: ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
70 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
62
61 to 58
57
H
reserved
DT
HW —
writes
-
HW —
writes
SW —
writes
Halt
: Transaction is halted.
-
Data Toggle
: Set the Data Toggle bit to start the PTD. Software writes the
current transaction toggle value. Hardware writes the next transaction toggle
value.
Error Counter
: This field corresponds to the Cerr[1:0] field in the QH. The
default value of this field is zero for isochronous transactions.
56 to 55
Cerr[1:0]
HW —
writes
SW —
writes
-
HW —
writes
54 to 47
46 to 32
reserved
NrBytes
Transferred
[14:0]
-
Number of Bytes Transferred
: This field indicates the number of bytes sent
or received for this transaction. If Mult[1:0] is greater than one, it is possible
to store intermediate results in this field.
DW2
31 to 24
23 to 8
reserved
DataStart
Address
[15:0]
-
SW —
writes
-
Data Start Address
: This is the start address for the data that will be sent or
received on or from the USB bus. This is the internal memory address and
not the direct CPU address.
RAM address = (CPU address
400h)/8
Bits 7 to 3 represent the polling rate for ms-based polling.
The INT polling rate is defined as 2
(b – 1)
μ
SOF, where b is 1 to 9.
When b is 1, 2, 3 or 4, use
μ
SA to define polling because the rate is equal to
or less than 1 ms. Bits 7 to 3 are set to 0. Polling checks
μ
SA bits for
μ
SOF
rates.
b
Rate
μ
Frame[7:3]
1
1
μ
SOF
0 0000
2
2
μ
SOF
0 0000
3
4
μ
SOF
0 0000
4
1 ms
0 0000
5
2 ms
0 0001
6
4 ms
0 0010 to 0 0011
7
8 ms
0 0100 to 0 0111
8
16 ms
0 1000 to 0 1111
9
32 ms
1 0000 to 1 1111
7 to 0
μ
Frame[7:0]
SW —
writes
μ
SA[7:0]
1111 1111
1010 1010 or 0101 0101
any 2 bits set
any 1 bit set
any 1 bit set
any 1 bit set
any 1 bit set
any 1 bit set
any 1 bit set
DW1
63 to 47
46
reserved
S
-
SW —
writes
-
This bit indicates if a split transaction has to be executed:
0 —
High-speed transaction
1 —
Split transaction.
Endpoint type
:
11 —
Interrupt.
Token
: This field indicates the token PID for this transaction:
00 —
OUT
01 —
IN.
45 to 44
EPType[1:0]
SW —
writes
43 to 42
Token[1:0]
SW —
writes
Table 68:
Bit
High-speed interrupt IN and OUT, QHP: bit description
…continued
Symbol
Access
Description
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