參數(shù)資料
型號(hào): ISP1761BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 137/158頁
文件大?。?/td> 724K
代理商: ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
137 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
15.1.2
DMA timing
In the following sections:
Polarity of DACK is active HIGH
Polarity of DREQ is active HIGH.
15.1.2.1
Single cycle: DMA read
t
w13
t
su13
t
su23
RD_N pulse width
CS_N setup time before RD_N LOW
address setup time before RD_N LOW
t
d13
0
0
-
-
-
ns
ns
ns
Table 167: Memory read
…continued
V
CC(I/O)
= 3.3 V to 3.6 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
Min
Max
Unit
Fig 23. DMA read (single cycle)
Table 168: DMA read (single cycle)
V
CC(I/O)
= 1.65 V to 1.95 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
t
a14
DACK assertion time after DREQ assertion
t
a24
RD_N assertion time after DACK assertion
t
d14
data valid time after RD_N assertion
t
w14
RD_N pulse width
t
a34
DREQ deassertion time after RD_N assertion
t
a44
DACK deassertion to next DREQ assertion time
Min
0
0
-
t
d14
23
-
Max
-
-
24
-
-
56
Unit
ns
ns
ns
ns
ns
ns
Table 169: DMA read (single cycle)
V
CC(I/O)
= 3.3 V to 3.6 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
t
a14
DACK assertion time after DREQ assertion
t
a24
RD_N assertion time after DACK assertion
t
d14
data valid time after RD_N assertion
Min
0
0
-
Max
-
-
20
Unit
ns
ns
ns
004aaa530
DATA
DREQ
DACK
RD_N
t
a14
t
a24
t
d14
t
w14
t
a44
t
a34
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