參數(shù)資料
型號： ISP1761BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 113/158頁
文件大小： 724K
代理商： ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
113 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.5.7
Endpoint Type register (R/W: 0208h)
This register sets the endpoint type of the indexed endpoint: isochronous, bulk or
interrupt. It also serves to enable the endpoint and configure it for double buffering.
Automatic generation of an empty packet for a zero-length TX buffer can be disabled using
bit NOEMPKT. The register contains 2 B, and the bit allocation is shown in
Table 117
.
[1]
The reserved bits should always be written with the reset value.
10.6 DMA registers
The Generic DMA (GDMA) transfer can be done by writing the proper opcode in the DMA
Command register. The control bits are given in
Table 119
.
GDMA read or write (opcode = 00h/01h) for the Generic DMA slave mode
Table 117: Endpoint Type register: bit allocation
Bit
15
Symbol
Reset
0
Bus reset
0
Access
Bit
7
Symbol
Reset
0
Bus reset
0
Access
R/W
14
13
12
11
10
9
8
reserved
[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
ENDPTYP[1:0]
0
0
R/W
0
reserved
[1]
0
0
R/W
NOEMPKT
0
0
R/W
ENABLE
0
0
R/W
DBLBUF
0
0
R/W
0
0
0
0
R/W
R/W
Table 118: Endpoint Type register: bit description
Bit
Symbol
15 to 5
-
4
NOEMPKT
Description
reserved
No Empty Packet:
Logic 0 causes an empty packet to be appended to
the next IN token of the USB data, if the Buffer Length register or the
Endpoint MaxPacketSize register is zero. Logic 1 disables this function.
This bit is applicable only in the DMA mode.
Endpoint Enable
: Logic 1 enables the FIFO of the indexed endpoint.
The memory size is allocated as specified in the Endpoint
MaxPacketSize register. Logic 0 disables the FIFO.
Remark:
‘Stall’ing a data endpoint will confuse the Data Toggle bit on
the stalled endpoint because the internal logic starts from where it has
stalled. Therefore, the Data Toggle bit must be reset by disabling and
re-enabling the corresponding endpoint (by setting bit ENABLE to
logic 0 or logic 1 in the Endpoint Type register) to reset the PID.
Double Buffering:
Logic 1 enables double buffering for the indexed
endpoint. Logic 0 disables double buffering.
ENDPTYP[1:0]
Endpoint Type:
These bits select the endpoint type as follows.
00 —
not used
01 —
Isochronous
10 —
Bulk
11 —
Interrupt.
3
ENABLE
2
DBLBUF
1 to 0
相關PDF資料
PDF描述
ISP1761ET Hi-Speed Universal Serial Bus On-The-Go controller
ISP2100A Telecommunication IC
ISP2100BN4 Microprocessor
ISP2300 Controller Miscellaneous - Datasheet Reference
ISP2310 Controller Miscellaneous - Datasheet Reference
相關代理商/技術參數(shù)
參數(shù)描述
ISP1761BE,518 功能描述:USB 接口集成電路 USB HS OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761BE,551 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761BE,557 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761BE518 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB OTG 128LQFP
ISP1761BEGE 功能描述:IC USB CTRL HI-SPEED 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*