參數(shù)資料
型號(hào)： ISP1761BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 118/158頁
文件大小： 724K
代理商： ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
118 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.6.5
DMA Interrupt Reason register (R/W: 0250h)
This 2 B register shows the source(s) of DMA interrupt. Each bit is refreshed after a DMA
command is executed. An interrupt source is cleared by writing logic 1 to the
corresponding bit. When the register is read, perform a logical AND with the
corresponding bits of the DMA Interrupt Enable register.
The bit allocation is given in
Table 129
.
[1]
The reserved bits should always be written with the reset value.
Table 128: DMA Hardware register: bit description
Bit
Symbol
Description
7 to 6
ENDIAN[1:0]
Endian
: These bits determine whether the data bus is swapped between
the internal RAM and the DMA bus.
00 —
Normal data representation
16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0]
01 —
Swapped data representation
16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8]
10, 11 —
reserved.
5
EOT_POL
Selects the polarity of the End-Of-Transfer input; used in GDMA (slave)
mode only.
0 —
EOT is active LOW
1 —
EOT is active HIGH.
4
-
reserved
3
DACK_POL
DACK Polarity
: Selects the DMA acknowledgment polarity.
0 —
DACK is active LOW
1 —
DACK is active HIGH.
2
DREQ_POL
DREQ Polarity
: Selects the DMA request polarity.
0 —
DREQ is active LOW
1 —
DREQ is active HIGH.
1 to 0
-
reserved
Table 129: DMA Interrupt Reason register: bit allocation
Bit
15
Symbol
14
13
12
11
10
9
8
reserved
GDMA_
STOP
0
0
R/W
4
reserved
INT_EOT
reserved
[1]
DMA_
XFER_OK
0
0
R/W
0
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
0
0
0
0
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
reserved
[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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