
IBM3206K0424
IBM Processor for Network Resources
Preliminary
ATM PHY Bus Interface
Page 54 of 676
pnr25.chapt02.01
August 14, 2000
1
FYTEOP
Output
PHY Transmit EOP
When using an external POS-PHY, this signal indicates if the 
FYTDATA (15-0) contains the last data of a packet. If the exter-
nal PHY is not a POS-PHY, this signal should ignored.
1
FYRMOD
Input
PHY Receive MOD
When using an external POS-PHY, this signal indicates if the 
FYRDATA (7-0) contains valid data. If FYRMOD is 
’
1
’
, FYR-
DATA(7-0) is ignored. FYRMOD is only relevant when 
FYREOP is 
’
1
’
. A value of 
’
1
’
 any other time will be ignored. If a 
POS-PHY is not connected, this signal should be tied to GND.
1
FYTMOD
Output
PHY Transmit MOD
When using an external POS-PHY, this signal indicates if the 
FYTDATA (7-0) contains valid data. If FYTMOD is 
’
1
’
, FYR-
DATA(7-0) will be ignored. FYTMOD is only driven to a 
’
1
’
when FYTEOP is 
’
1
’
.
2
 FYTSDATP/N
Output
 SERDES Transmit Data 
(Differential)
When using the internal framer and the internal SERDES, 
these signals provide the serial transmit data stream. When the 
transmit side of LINKC is connected to an Echo interface, this 
differential driver will provide the clock that goes with the data 
FYRDAT(7-0), parity FYTPAR(7-0), and SOC FYTSOC.
2
 FYTSCLKP/N
 Input
SERDES Transmit Clock 
(Differential)
When using the internal framer and the internal SERDES, the 
reference 155.52MHz clock is supplied on these signals. When 
not in use, these should be tied to (TBD).
2
 FYRSDATP/N
 Input
SERDES Receive Data 
(Differential)
When using the internal framer and the internal SERDES, the 
recovered receive data is supplied on these signals. When not 
in use, these should be tied to (TBD).
2
 FYRSCLKP/N
 Input
SERDES Receive Clock 
(Differential)
When using the internal framer and the internal SERDES, the 
recovered 155.52MHz clock is supplied on these signals. 
When not in use, these should be tied to (TBD).
1
 FYDTCT
 Input
PHY Carrier Detect
When using an external PHY, the PHY uses this signal to indi-
cate carrier detect. When using the internal framer, this signal 
provides the deserializer lock detect signal, ELockDet, from the 
deserializer.
1
 FYDISCRD
Input
 PHY Cell Discard
When using an external PHY, this signal causes the current 
cell being received to be discarded. In this case it should only 
be asserted for the duration of one of the 53 bytes of the ATM 
cell. When using the internal framer, this signal provides the 
optical/electrical module Loss-Of-Signal indication, LossSig.
PHY Bus Pin Descriptions 
 (Page 3 of 3)
Quantity
Pin Name
Input/Output
Pin Function
Pin Description
Note:  
Because some of the PHY transmit I/Os are used for receive framer functions and vice versa, there are some restrictions on how 
the interfaces can be used.
1. If the transmit path is using an external PHY and the receive path is using the internal framer, FYTPAR(1) will assume the OOF 
function and not be available as a parity output. This is only a concern if the PHY uses a 16-bit data interface and parity is being 
used.
2. If the receive path is using an external PHY and the transmit path is using the internal framer, FYRPAR(1) will assume the OFPtx-
LPow function and not be available as a parity input. This is only a concern if the PHY uses a 16-bit data interface.
3. If the transmit path is using an external PHY and the receive path is using the internal framer, and the external PHY has a 16-bit 
data interface, then the receive HDLC interface cannot be used. The three I/O for the RX HDLC interface will instead take on the 
function of FYTDAT(15-13).