
IBM3206K0424
Preliminary 
IBM Processor for Network Resources
nrm.toc.01
August 14, 2000
Page 11
RXQUE Dequeue Registers ..........................................................................................................390
RXQUE Enqueue Registers ..........................................................................................................391
RXQUE Next Lower Bound Registers ...........................................................................................392
RXQUE Last Event Dropped Register ...........................................................................................393
RXQUE Timestamp Register .........................................................................................................393
RXQUE Timestamp Pre-Scaler Register .......................................................................................393
RXQUE Timestamp Shift Register ................................................................................................394
RXQUE Event Routing Registers ..................................................................................................394
RXQUE Event Latency Timer Register .........................................................................................395
RXQUE Queues Status Register ...................................................................................................396
RXQUE Interrupt Enable Registers ...............................................................................................397
RXQUE Status and Enabled Status Registers ..............................................................................398
RXQUE Control Register ...............................................................................................................400
Debugging Register Access ..........................................................................................................401
RXQUE RXQ State Machine Variable Register ............................................................................401
RXQUE RXQ ENQ State Machine Variable Register ....................................................................401
RXQUE Enq FIFO Head Ptr Register ............................................................................................402
RXQUE Enq FIFO Tail Ptr Register ..............................................................................................402
RXQUE Enq FIFO Array ................................................................................................................402
PHY Level Interfaces ...................................................................................................403
The PHY Interface (LINKC) ................................................................................................................403
Functional Description ...................................................................................................................403
Multi-Drop ......................................................................................................................................403
POS-PHY ......................................................................................................................................403
Moving Cells To and From the IBM3206K0424 .............................................................................404
LINKC Global Control Register ......................................................................................................404
LINKC Configuration 0 Transmit & Receive Control Register .......................................................407
LINKC Configuration 1 Transmit & Receive Control Register .......................................................410
LINKC Configuration 2 Transmit & Receive Control Register .......................................................413
LINKC Configuration 3 Transmit & Receive Control Register .......................................................416
LINKC Map Transmit Configurations to Port Addresses ...............................................................419
LINKC Map Receive Configurations to Port Addresses ................................................................420
LINKC Transmitted HEC Control Byte ...........................................................................................421
LINKC Interrupt/Status Register ....................................................................................................422
LINKC Interrupt Enable Register ...................................................................................................424
LINKC Prioritized Interrupts ...........................................................................................................424
LINKC Transmit State Machine Register .......................................................................................425
LINKC Receive State Machine Register ........................................................................................425
LINKC LAN Address Register .......................................................................................................426
LINKC Canonical LAN Address Register ......................................................................................426
LINKC Passed TX Data Register ..................................................................................................427
Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization 
from EPROM Data ........................................................................................................................428
NPBUS Control Register ...............................................................................................................428
NPBUS Status Register .................................................................................................................431
NPBUS Interrupt Enable Register .................................................................................................432
NPBUS EPROM Address/Command Register ..............................................................................433
NPBUS EPROM Data Register .....................................................................................................434
PHY 1 Registers ............................................................................................................................434
PHY 2 Registers ............................................................................................................................434