
IBM3206K0424
IBM Processor for Network Resources
Preliminary
The IOP Bus Specific Interface Controller (PCINT)
Page 116 of 676
pnr25.chapt04.01
August 14, 2000
1.17: PCINT 64-bit Control Register
This register contains miscellaneous control bits.
Length
9 bits
Type
Read/Write
Address
XXXX 0078
Restrictions
Can be written or read during configuration cycle, memory cycle when enabled (see 
PCINT Base Address Control Register on page 111
), or an I/O cycle. This register 
is documented as big endian, but how data is presented on the PCI bus depends 
on how the controls are set in the PCINT Endian Control Register.
Power on Reset Value 
(Big Endian)
X
’
00000XXX
’
, where the 'X' values depend on whether bit 0 is set and values of the 
enable bits in PCINT 64-bit Enable Register.
Power on Reset Value 
(Little Endian)
X
’
XX0X0000
’
, where the 'X' values depend on whether bit 0 is set and values of the 
enable bits in PCINT 64-bit Enable Register.
E
E
E
E
E
P
E
E
6
8
7
6
5
4
3
2
1
0
Bit(s)
Name
Description
8
Enable Master 64-bit Data path
This bit set to 
‘
1
’
 will enable master 64-bit data path for dma transfers.
7
Enable Master 64-bit Addressing
This bit set to 
‘
1
’
 will enable master 64-bit addressing.
6
Enable Slave Register Swap Word 
mode
This bit set to 
‘
1
’
 will enable word swapping of the each of the four groups of data 
bytes in an eight-byte register transfer. 2
5
Enable Slave 64-bit Data Path
This bit set to 
‘
1
’
 will enable the slave 64-bit data path for registers and Packet Mem-
ory.
4
Enable Slave 64-bit Addressing 
This bit set to 
‘
1
’
 will enable slave 64-bit addressing, making base addresses 1 and 2 
available for register accesses (memory cycles only) and base addresses 3 and 4 
available for Packet Memory. 
3
PCI AD(63-32) Driver Control
This bit set to 
‘
1
’
 will cause the AD(63-32) PCI drivers to force to tri-state unless a 
64-bit access is occurring. Otherwise, when set to 
‘
0
’
, the drivers will always drive 
active.
2
Enable Slave Memory Swap Word 
mode
This bit set to 
‘
1
’
 will enable word swapping of the each of the four groups of data 
bytes in an eight-byte slave memory transfer through BCACH. 2