
IBM3206K0424
Preliminary 
IBM Processor for Network Resources
nrm.toc.01
August 14, 2000
Page 15
Sonet Framer Core (FRAMR Chiplet Address Mapping) ..........................................525
GPPINT Architecture ..........................................................................................................................525
Overview ........................................................................................................................................525
Reset Register ...............................................................................................................................525
Interrupt Registers .........................................................................................................................525
Handshaking Error Registers ........................................................................................................526
Clock Monitor Status Registers .....................................................................................................526
Local Gppint Configuration Registers ............................................................................................526
Global Static Configuration Registers ............................................................................................526
Status Registers ............................................................................................................................526
GPPINT Register Description ............................................................................................................528
Chiplet Reset Register (RESGP) ...................................................................................................528
Chiplet Interrupt and Mask Registers (IRQGP1 (IRMGP1)) ..........................................................529
Handshaking Error Indication and Mask Registers (HShake1) .....................................................530
Clock Monitor Status and Mask Registers (ClkStat1 (ClkMask1)) ................................................531
Clock Monitor Test Period Register (CMonGP1) ...........................................................................532
Watchdog Timer Period Register (WDTGP1) ................................................................................532
GPPINT Local Configuration Registers (ConfGP1) .......................................................................533
Vital Macro Data Register (VPD) ...................................................................................................534
Static Configuration Register (GATMCS) ......................................................................................534
GCasc ............................................................................................................................................535
GLoopTx ........................................................................................................................................535
GLoopRx .......................................................................................................................................536
GExtRes ........................................................................................................................................536
OFPTXGP .....................................................................................................................................537
OFPRXGP1 ...................................................................................................................................537
OFPRXGP2 ...................................................................................................................................538
PIMRConf2 ....................................................................................................................................538
SIMStat ..........................................................................................................................................539
GPPHandler Architecture ..................................................................................................................540
Overview ........................................................................................................................................540
Counter Registers ..........................................................................................................................540
Reset Registers .............................................................................................................................540
Command Registers ......................................................................................................................540
Event Latch Registers ...................................................................................................................541
Interrupt Registers .........................................................................................................................541
Configuration Registers .................................................................................................................541
Register Types ..............................................................................................................................541
ATM Cell Handler Architecture : Transmit Direction ......................................................................542
ACH Tx Register Description ............................................................................................................543
Counter Registers ..........................................................................................................................543
ROFmid .........................................................................................................................................543
ROFhi ............................................................................................................................................543
ACBC .............................................................................................................................................544
IUC ................................................................................................................................................544
ACBE .............................................................................................................................................545
ACBETh11 .....................................................................................................................................546
CntEn1 ...........................................................................................................................................546
Reset Register (RESET) ...............................................................................................................547
Status Registers ............................................................................................................................548
STAT1 ...........................................................................................................................................548