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參數(shù)資料
| 型號： | AM8530 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 71/194頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530 |
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Data Communication Modes Functional Description
AMD
4–19
i.
The Status x11 will be reported when the first special conditions is received.
ii. As more data is received, the status will switch to x10 to reflect that a Receiver
interrupt has been received, but that the present data in the Receive Data 3-byte
FIFO does not contain a special condition.
iii. when a special condition resides at the top of the Receive Data FIFO, the status
x11 will be reported.
4.7.1.3.6
Am85C30 Aborted Frame Handling When Using The 10x19 Frame
Status FIFO
Field feedback on the Am85C30 Frame Status FIFO has revealed that neither AMD nor
competition create an entry in the Frame Status FIFO when a frame being received is
aborted (seven or more consecutive 1s appear in the receive Data stream). An aborted
frame indicates to the receiver that synchronization has been lost. the receiver then en-
ters “Hunt Mode” where it monitors the input data stream until a SDLC flag is recognized.
After an SDLC flag is received, the receiver is capable of receiving additional data
frames.
Because of the lack of an entry in the Frame Status FIFO for aborted frames, the receiver
cannot look only at the Frame Status FIFO to determine the exact nature of all data re-
ceived. To properly recognized and recover from aborted frames, the following practice is
recommended:
1. The receiver must enable an external/status interrupt on ABORT.
2. When an interrupt due to an ABORT is received, all frames contained in the Frame
Status FIFO should be considered to be corrupted and discarded. The processor
should request re-transmission of these frames.
3. Note that an external/status interrupt will be generated both when an ABORT is
received and when the ABORT condition disappears. Either transition of the ABORT
status will cause the ABORT bit in Read Register 0 to latch until a “Reset External/
Status Interrupt” command is issued through Write Register 0.
This behavior is identical on both competition and AMD product and is not revision de-
pendent.
4.7.1.4
The first 8-bit non-flag character following the opening flag of a frame is assumed by the
SCC to be the address of the station for which the frame is intended. The SCC provides
several options for handling this address via bits D2 (Address Search mode) and D1
(SYNC Character Load Inhibit) of WR3.
Address Search Mode
If the Address Search mode is enabled, the receiver’s address recognition logic will be
enabled and the receiver will compare the first 8-bit non-flag character with the contents
of WR6. If these two characters match, or if the received character is the global address
(all ‘1’s), data are passed to the Receive Shift Register and character assembly begins. If
no match is detected the receiver remains in Hunt mode and no data are passed to the
Receive Shift Register. The global address is used in applications where a specific station
address is not known, as might be the case in a switched connection, or when a broad-
cast frame is sent to all stations. Address Search mode will be enabled when WR3 is pro-
grammed as shown below.
X
1
0
D7
D6 D5
D4 D3
D2 D1
D0
WR3—Register Layout
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM8530H | Serial Communications Controller |
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530ADC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530ADCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530AJC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530APC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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