- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366552 > AM8530 (Advanced Micro Devices, Inc.) Serial Communications Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM8530 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 178/194頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁當(dāng)前第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁
SCC Application Notes
AMD
7–29
ACD
is asserted whenever the receiver detects line activity. This scheme is a significant
asset in the single bus (half-duplex) architecture shown in Figure 7–19. Consider the case
where Device 1 is transmitting and Device 4 is receiving. Although the message on the
bus is not read by Devices 2 and 3, their respective
ACD
lines will be active (Low) due to
line activity at their receive inputs, RxL0 and RxL1. This prevents the controllers from
transmitting as long as there is line activity, thus avoiding any potential collisions or inter-
ruption of the transmission. During transmission,
ACD
is internally negated. The
ACD
and
RTS
gating scheme does not interfere with normal data transmission.
In this example (Figure 7–19), the Am7960 will generate and recognize its own preamble
because the Am8530H does not have that capability. This is called Mode 0 operation and
is accomplished by holding the Mode pin Low. The Master Reset input is an asynchro-
nous transceiver reset. When asserted, all interface signals will be inhibited with the ex-
ception of transmit clock. It has an internal pull-up resistor, internal discharge clamp
diode, and input hysteresis to provide power-on reset with a single external capacitor to
ground.
The Clear-To-Send (
CTS
) is activated just before the Am7960 is ready to transmit data.
The interface for Transmit Data (TxD), Transmit Clock (TxC), Receive Data (RxD), and
Carrier Sense (
CS
) between the Am7960 and the Am8530H are direct connections. This
ease of connection is possible because the Am8530 supports the modem-like interface
(standard for most USARTs and serial communications controllers) for which the Am7960
is designed.
The RxC rising edge to RxD valid time on the Am7960 varies from –5 ns to +20ns. The
Am8530H clocks in data on the rising edge of RxC and requires a set-up of at least 0 ns
from RxD to the rising edge of
RxC
. This set-up time will not be met if the same RxC
edge that clocks out data from the Am7960 is used to clock in data to the Am8530H. This
problem can be solved by inverting the receive clock from the Am7960 before feeding it
into the Am8530H.
The X1 and X2 pins supply the clock to the digital phase-locked loop in the Am7960,
which in turn generates the TxC and RxC signals. These inputs can be driven by either a
crystal or a TTL source. The crystal oscillator circuit must be used, in 3rd harmonic, for
frequencies above 24 MHz. If a TTL source is connected to X1, the X2 pin must be left
open.
The hardware connections between the Am8530H and a CPU and DMA controller are
equally simple. Use of a DMA controller is suggested for any system that transmits above
500 kb/s, to simplify data transfers between the memory and the Am8530H. After initializ-
ing the Am8530H and the DMA channel, the CPU leaves the actual transfer of data to the
DMA controller (explained under Software Considerations later in this application note).
During transmission, the SCC requests a DMA transfer by pulling the
W
/
REQ
line active
(Low) if the transmit buffer is empty, or keeps it High until the transmit buffer is empty.
Similarly, the receive section will request a DMA transfer if the receive buffer contains a
character or will keep
W
/
REQ
High until a character enters the receive buffer. A flag
within the SCC can be read to recognize an End-Of-Message (EOM).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM8530H | Serial Communications Controller |
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530ADC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530ADCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530AJC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530APC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。