Register Description
AMD
6–25
Bits 4 and 3: Transmit Clock 1 and 0
These bits determine the source of the transmit clock as shown in Table 6–7. They do not
interfere with any of the modes of operation of the SCC but simply control a multiplexer
just before the internal transmit clock input. The DPLL output that may be used to feed
the transmitter in FM modes lags by 90 the output of the DPLL used by the receiver. This
makes the received and transmitted bit cells occur simultaneously, neglecting delays. A
hardware reset selects the TRxC pin as the source of the transmit clocks.
Table 6–7. Transmit Clock Source
D
4
0
0
1
1
D
3
0
1
0
1
Transmit Clock = RTxC pin
Transmit Clock =
TRxC
pin
Transmit Clock = BRG output
Transmit Clock = DPLL output
Bit 2:
TRxC
O/I
This bit determines the direction of the TRxC pin. If this it is set to ‘1’, the
TRxC
pin is an
output and carries the signal selected by D1 and D0 of this register. However, if either the
receive or the transmit clock is programmed to come from the
TRxC
pin, TRxC will be an
input, regardless of the state of this bit. The
TRxC
pin is also an input if this bit is set to
‘0’. A hardware reset forces this bit to ‘0’.
Bits 1 and 0:
TRxC
Output Source 1 And 0
These bits determine the signal to be echoed out of the SCC via the
TRxC
pin. No signal
is produced if
TRxC
has been programmed as the source of either the receive or the
transmit clock. If
TRxC
O/I (bit 2) is set to ‘0’, these bits are ignored.
If the XTAL oscillator output is programmed to be echoed, and the XTAL oscillator has
not been enabled, the
TRxC
pin hoes High. The DPLL signal that is echoed is the DPLL
signal used by the receiver. Hardware reset selects the XTAL oscillator as the output
source.
Table 6–8. Transmit External Control Selection
D
1
0
0
1
1
D
0
0
1
0
1
TRxC
= XTAL oscillator output
TRxC
= Transmit Clock
TRxC
= BRG output
TRxC
= DPLL output