- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄366552 > AM8530 (Advanced Micro Devices, Inc.) Serial Communications Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM8530 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 142/194頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)當(dāng)前第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)
Register Description
AMD
6–32
The XTAL oscillator should not be selected in External Sync mode.
In Asynchronous mode, the operation of this bit is identical to that of the CTS status bit,
except that this bit reports the state of the
SYNC
pin.
In External sync mode the
SYNC
pin is used by external logic to signal character syn-
chronization. When the Enter Hunt Mode command is issued in External Sync mode, the
SYNC pin must be held High by external sync logic until character synchronization is
achieved. A High on the
SYNC
pin holds the Sync/Hunt bit in the reset condition.
When external synchronization is achieved,
SYNC
must be driven Low on the second
rising edge of the Receive Clock after the last rising edge of the Receive Clock on which
the last bit of the receive character was received. Once
SYNC
is forced Low, it is good
practice to keep it Low until the CPU informs the external sync logic that synchronization
has been lost or that a new message is about to start. Both transitions on the
SYNC
pin
case External/Status interrupts if the Sync/Hunt IE bit is set to ‘1’.
The Enter Hunt Mode command should be issued whenever character synchronization is
lost. At the same time, the CPU should inform the external logic that character synchroni-
zation has been lost and that the SCC is waiting for SYNC to become active.
In the Monosync and Bisync Receive modes, the Sync/Hunt status bit is initially set to ‘1’
by the Enter Hunt Mode command. The Sync/Hunt bit is reset when the SCC establishes
character synchronization. Both transitions cause External/Status interrupts if the Sync/
Hunt IE bit is set when the CPU detects the end of message or the loss of character syn-
chronization. When the CPU detects the end of message of the loss of character
synchronization, the Enter Hunt Mode command should be issued to set the Sync/Hunt
bit and cause an External/Status interrupt. In this mode, the
SYNC
pin is an output, which
goes Low every time a sync pattern is detected in the data stream.
In the SDLC modes, the Sync/Hunt bit is initially set by the Enter Hunt Mode command or
when the receiver is disabled. It is reset when the opening flag of the first frame is de-
tected by the SCC. An External/Status interrupt is also generated if the Sync/Hunt IE bit is
set. Unlike the Monosync and Bisync modes, once the Sync/Hunt bit is reset in SDLC
mode, it does not need to be set when the end of the frame is detected. The SCC auto-
matically maintains synchronization. The only way the Sync/Hunt bit can be set again is
by the Enter Hunt Mode command or by disabling the receiver.
Bit 3: Data Carrier Detect
If the DCD IE bit in WR 15 is set, this bit indicates the state of the
DCD
pin the last time
the Enabled External/Status bits changed. Any transition on the
DCD
pin while no inter-
rupt is pending latches the state of the
DCD
pin and generates an External/Status inter-
rupt. Any odd number of transitions on the
DCD
pin while another External/Status
interrupt is pending also causes an External/Status interrupt condition. If the DCD IE is
reset, this bit merely reports the current, unlatched state of the
DCD
pin.
Bit 2: TX Buffer Empty
This bit is set to ‘1’ when the transmit buffer is empty. It is reset while CRC is sent in a
synchronous or SDLC mode and while the transmit buffer is full. The bit is reset when a
character is loaded into the transmit buffer. This bit is always in the set condition after a
hardware or channel reset.
Bit 1: Zero Count
If the Zero Count Interrupt Enable bit is set in WR15, this bit is set to one while the
counter in the baud rate generator is at the count zero. If there is no other External/Status
interrupt condition pending at the time this bit is set, an External/Status interrupt is gener-
ated. However, if there is another External/Status interrupt pending at this time, no inter-
rupt is initiated until interrupt service is complete. If the Zero Count condition does not
persist beyond the end of the interrupt service routine, no interrupt will be generated. This
bit is not latched High, even though the other External/Status latches close as a result of
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM8530H | Serial Communications Controller |
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530ADC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
| AM8530ADCB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
| AM8530AJC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
| AM8530APC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
| AM8530DC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。