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參數(shù)資料
| 型號： | AM8530 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 104/194頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530 |
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Support Circuitry Programming
AMD
5–10
5.4.3
In FM1 encoding, also known as biphase mark, a transition is present on every bit cell
boundary, and an additional transition may be present in the middle of the bit cell. In FM1,
a ‘0’ is sent as no transition in the center of the bit cell and a ‘1’ is sent as a transition in
the center of the bit cell. FM1 encoded data contains sufficient information to recover a
clock from the data.
FM1 (Biphase Mark)
5.4.4
In FM0 encoding, also known as biphase space, a transition is present on every bit cell
boundary and an additional transition may be present in the middle of the bit cell. In FM0
a ‘1’ is sent as no transition in the center of the bit cell and a ‘0’ is sent as a transition in
the center of the bit cell. FM0 encoded data contains sufficient information to recover a
clock from the data.
FM0 (Biphase S pac e)
5.4.5
In addition to these four methods, the SCC can be used to decode Manchester (biphase
level) data using the DPLL in the FM mode and programming the receiver for NRZ data.
Manchester encoding always produces a transition at the center of the bit cell. If the tran-
sition is High-to-Low, the bit is a ‘1’; if the transition is Low-to-High, the bit is a ‘0’.
Manc hester Dec oding
5.4.6
The data encoding method to be used should be selected in the initialization procedure
before the transmitter and receiver are enabled but no other restrictions apply. Note, in
Figure 5–4, that in NRZ and NRZI the receiver samples the data only on one edge. How-
ever, in FM1 and FM0, the receiver samples the data on both edges. Also, as shown in
Figure 5–4, the transmitter defines bit cell boundaries by one edge in all cases and uses
the other edge in FM1 and FM0 to create the mid-bit transition.
Data Enc oding Programming
5.5
The SCC contains a DPLL that can be used to recover clock information from a data
stream with NRZI or FM coding. The DPLL is driven by a clock that is nominally 32
(NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with the data
stream, to construct a receive clock for the data. This clock can then be used as the re-
ceive clock, the transmit clock, or both.
DIGIT AL PHAS E-LOCK ED LOOP (DPLL)
Figure 5–5 shows a block diagram of the DPLL. It consists of a 5-bit counter, an edge
detector, and a pair of output decoders. The clock for the DPLL comes from the output of
a two-input multiplexer, and the two outputs go to the transmitter and receive clock multi-
plexers. The DPLL is controlled by seven commands that are encoded in bits D7, D6, and
D5 of WR14.
Edge Detector
RxD
Receive
Clock
Decode
Count Modifier
5-Bit Counter
Transmit
Clock
Decode
Figure 5–5. DPLL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530ADC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530ADCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530AJC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530APC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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