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| 型號： | AD9910BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 1GSPS 14BIT PAR 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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Data Sheet
AD9910
Rev. D | Page 17 of 64
THEORY OF OPERATION
The AD9910 has four modes of operation.
Single tone
RAM modulation
Digital ramp modulation
Parallel data port modulation
The modes relate to the data source used to supply the DDS
with its signal control parameters: frequency, phase, or ampli-
tude. The partitioning of the data into different combinations
of frequency, phase, and amplitude is handled automatically
based on the mode and/or specific control bits.
In single tone mode, the DDS signal control parameters come
directly from the programming registers associated with the
serial I/O port. In RAM modulation mode, the DDS signal
control parameters are stored in the internal RAM and played
back upon command. In digital ramp modulation mode, the
DDS signal control parameters are delivered by a digital ramp
generator. In parallel data port modulation mode, the DDS
signal control parameters are driven directly into the parallel port.
The various modulation modes generally operate on only one of
the DDS signal control parameters (two in the case of the polar
modulation format). The unmodulated DDS signal control
parameters are stored in their appropriate programming
registers and automatically route to the DDS based on the
selected mode.
A separate output shift keying (OSK) function is also available.
This function employs a separate digital linear ramp generator
that only affects the amplitude parameter of the DDS. The OSK
function has priority over the other data sources that can drive
the DDS amplitude parameter. As such, no other data source
can drive the DDS amplitude when the OSK function is enabled.
Although the various modes (including the OSK function) are
described independently, they can be enabled simultaneously.
This provides an unprecedented level of flexibility for generating
complex modulation schemes. However, to avoid multiple data
sources from driving the same DDS signal control parameter,
the device has a built-in priority protocol (see Table 5 in the
Mode Priority section).
SINGLE TONE MODE
In single tone mode, the DDS signal control parameters are
supplied directly from the programming registers. A profile is
an independent register that contains the DDS signal control
Each profile is independently accessible. Use the three external
profile pins (PROFILE[2:0]) to select the desired profile. A
change in the state of the profile pins with the next rising edge
on SYNC_CLK updates the DDS with the parameters specified
by the selected profile.
06479-
005
16
PARALLEL
INPUT
PDCLK
SCLK
SDIO
I/O_RESET
PROFILE[2:0]
I/O_UPDATE
RAM
POWER-
DOWN
CONTROL
E
X
T
_P
W
R_DW
N
DAC_RSET
IOUT
CS
TxENABLE
DAC FSC
OSK
A
θ
INVERSE
SINC
FILTER
CLOCK
AMPLITUDE (A)
FREQUENCY
(ω)
PHASE (θ)
DIGITAL
RAMP
GENERATOR
8
DAC FSC
8
2
MULTICHIP
SYNCHRONIZATION
SYSCLK
PLL
÷2
CL
O
CK
M
O
DE
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND
CONTROL
SER
IA
L
I/O
P
OR
T
2
AD9910
PROGRAMMING
REGISTERS
OUTPUT
SHIFT
KEYING
DATA
ROUTE
AND
PARTITION
CONTROL
3
INTERNAL CLOCK TIMING
AND CONTROL
ω
Acos (ωt + θ)
Asin (ωt + θ)
SYN
C
_
SMP_
ER
R
S
Y
NC_O
UT
S
Y
NC_I
N
P
LL_
LOC
K
P
LL_
LOOP
_
FI
L
T
ER
MA
ST
ER
_
R
ESET
2
AUX
DAC
8-BIT
DAC
14-BIT
DDS
RAM_SWP_OVR
DRCTL
DRHOLD
DROVER
S
Y
NC_CL
K
Figure 22. Single Tone Mode
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參數(shù)描述 |
|---|---|
| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9911 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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