參數(shù)資料
型號(hào)： AD9910BSVZ
廠商： Analog Devices Inc
文件頁數(shù)： 32/64頁
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
AD9910
Data Sheet
Rev. D | Page 38 of 64
WAVEFORM START
ADDRESS 0
WAVEFORM END
ADDRESS 0
WAVEFORM START
ADDRESS 1
WAVEFORM END
ADDRESS 1
06479-
026
1
RAM_SWP_OVER
RAM PROFILE
RAM
ADDRESS
I/O_UPDATE
0
1
0
1
2
3
4
5
6
7
8
9
10
11
Δt0
Δt1
1
Figure 45. Internal Profile Control Timing Diagram (Continuous)
Internal Profile Control Continuous Waveform Timing
Diagram
An example of an internal profile control continuous waveform
timing diagram is shown in Figure 45. The diagram assumes that
the internal profile control bits (in Control Function Register 1)
are programmed as 1000. It also assumes that the start address in
RAM Profile 1 is greater than the end address in RAM Profile 0.
The gray bar across the top indicates the time interval over
which the designated profile is in effect. The circled numbers
indicate specific events.
Event 1—An I/O update registers that the internal profile
control bits (in Control Function Register 1) are programmed
to 1000. The RAM_SWP_OVR pin is set to Logic 0. The state
machine is initialized to the waveform start address of RAM
Profile 0 and begins incrementing through the address range for
RAM Profile 0 at intervals of Δt0 (as specified by the address
step rate for RAM Profile 0).
Event 2—The state machine reaches the waveform end address
of RAM Profile 0, and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 3—Having reached the waveform end address of RAM
Profile 0, the next expiration of the internal timer causes the
state machine to advance to RAM Profile 1. The state machine
is initialized to the waveform start address of RAM Profile 1
and begins incrementing through the address range for RAM
Profile 1 at intervals of Δt1.
Event 4—The state machine reaches the waveform end address
of RAM Profile 1, and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 5—Having reached the waveform end address of RAM
Profile 1, the next expiration of the internal timer causes the
state machine to jump back to RAM Profile 0. The state
machine initializes to the waveform start address of RAM
Profile 0 and begins incrementing through the address range for
RAM Profile 0 at intervals of Δt0.
Event 5 to Event 11—These events repeat indefinitely until the
internal profile control bits are reprogrammed and an I/O
update is asserted.
RAM Bidirectional Ramp Mode
In bidirectional ramp mode, upon assertion of an I/O update,
the RAM begins operating as a waveform generator using the
parameters programmed only into RAM Profile 0 (unlike ramp
up mode, which uses all eight profiles). Data is extracted from
RAM over the specified address range and at the specified rate
contained in the waveform start address, waveform end address,
and address ramp rate values of the selected RAM profile. The
data is delivered to the specified DDS signal control parameter(s)
based on the RAM playback destination bits.
The PROFILE[2:1] pins are ignored by the internal logic in this
mode. When a RAM profile programmed to operate in this
mode is selected, no other RAM profiles can be selected until the
active RAM profile is reprogrammed with a different RAM
operating mode. The no-dwell high bit is ignored in this mode.
With the bidirectional ramp mode activated via an I/O update
or profile change, the internal state machine readies to extract
data from the RAM at the waveform start address. Data extrac-
tion begins when PROFILE0 is Logic 1, which instructs the state
machine to begin incrementing through the address range. As
long as the PROFILE0 pin remains Logic 1, the state machine
continues to extract data until it reaches the waveform end
address. At this point, the state machine halts until the PROFILE0
pin is Logic 0, instructing the state machine to begin decrementing
through the address range. As long as the PROFILE0 pin is
Logic 0, the state machine continues to extract data until it
reaches the waveform start address. At this point, the state
machine halts until the PROFILE0 pin is Logic 1.
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