參數(shù)資料
型號: AD9910BSVZ
廠商: Analog Devices Inc
文件頁數(shù): 1/64頁
文件大?。?/td> 0K
描述: IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
1 GSPS, 14-Bit, 3.3 V CMOS
Direct Digital Synthesizer
Data Sheet
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2007–2012 Analog Devices, Inc. All rights reserved.
FEATURES
1 GSPS internal clock speed (up to 400 MHz analog output)
Integrated 1 GSPS, 14-bit DAC
0.23 Hz or better frequency resolution
Phase noise ≤ 125 dBc/Hz @ 1 kHz offset (400 MHz carrier)
Excellent dynamic performance with
>80 dB narrow-band SFDR
Serial input/output (I/O) control
Automatic linear or arbitrary frequency, phase, and
amplitude sweep capability
8 frequency and phase offset profiles
Sin(x)/(x) correction (inverse sinc filter)
1.8 V and 3.3 V power supplies
Software and hardware controlled power-down
100-lead TQFP_EP package
Integrated 1024 word × 32-bit RAM
PLL REFCLK multiplier
Parallel datapath interface
Internal oscillator can be driven by a single crystal
Phase modulation capability
Amplitude modulation capability
Multichip synchronization
APPLICATIONS
Agile local oscillator (LO) frequency synthesis
Programmable clock generators
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
Polar modulators
Fast frequency hopping
FUNCTIONAL BLOCK DIAGRAM
14-BIT DAC
1GSPS DDS CORE
LINEAR
RAMP
GENERATOR
1024-
ELEMENT
RAM
HIGH SPEED PARALLEL
DATA INTERFACE
TIMING AND CONTROL
SERIAL CONTROL
DATA PORT
REFCLK
MULTIPLIER
06479-
001
AD9910
Figure 1.
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