參數(shù)資料
型號(hào)： AD9910BSVZ
廠商： Analog Devices Inc
文件頁數(shù)： 33/64頁
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
Data Sheet
AD9910
Rev. D | Page 39 of 64
06479-
027
WAVEFORM START ADDRESS
WAVEFORM END ADDRESS
1
PROFILE0
RAM ADRESS
RAM_SWP_OVER
I/O_UPDATE
1
2
3
4
5
6
7
8
Δt
M DDS CLOCK CYCLES
Figure 46. Bidirectional Ramp Timing Diagram
If the PROFILE0 pin changes states before the state machine
reaches the programmed start or end address, the internal timer
is restarted and the direction of the address counter is reversed.
Figure 46 is a graphic representation of the bidirectional ramp
mode. It shows the action of the state machine in response to
the PROFILE0 pin and the response of the RAM_SWP_OVR pin.
The RAM_SWP_OVR pin switches to Logic 1 when the state
machine reaches the waveform end address. It remains Logic 1
until the state machine reaches the waveform start address and
the PROFILE0 pin transitions from Logic 0 to Logic 1.
The circled numbers in Figure 46 indicate specific events as
follows:
Event 1—An I/O update or profile change activates the RAM
bidirectional ramp mode. The state machine initializes to the
waveform start address, and the RAM_SWP_OVR pin is set to
Logic 0.
Event 2—Pin PROFILE0 switches to Logic 1. The state machine
begins incrementing the RAM address counter.
Event 3—Pin PROFILE0 remains at Logic 1 long enough for the
state machine to reach the waveform end address. The RAM_
SWP_OVR pin switches to Logic 1 accordingly.
Event 4—Pin PROFILE0 switches to Logic 0. The state machine
begins decrementing the RAM address counter. The RAM_
SWP_OVR pin remains at Logic 1.
Event 5—Pin PROFILE0 switches to Logic 1. The state machine
resets its internal timer and reverses the direction of the RAM
address counter (that is, it starts to increment). There is no
change of the RAM_SWP_OVR state because the waveform
start address has not yet been reached.
Event 6—Pin PROFILE0 switches to Logic 0. The state machine
resets its internal timer and again reverses the direction of the RAM
address counter. The RAM_SWP_OVR state does not change.
Event 7—Pin PROFILE0 remains at Logic 0 long enough for the
state machine to reach the waveform start address. There is no
change in the RAM_SWP_OVR state.
Event 8—Pin PROFILE0 switches to Logic 1. The state machine
resets its internal timer and begins incrementing the RAM
address counter. The RAM_SWP_OVR pin switches to Logic 0
because both the waveform start address was reached and the
PROFILE0 pin transitioned from Logic 0 to Logic 1.
RAM Continuous Bidirectional Ramp Mode
In continuous bidirectional ramp mode, upon assertion of an
I/O update or a change of profile, the RAM begins operating
as a waveform generator using the parameters programmed
into the RAM profile designated by the PROFILEx pins. Data is
extracted from RAM over the specified address range and at the
specified rate contained in the waveform start address, waveform
end address, and address ramp rate values of the selected RAM
profile. The data is delivered to the specified DDS signal control
parameter(s) based on the RAM playback destination bits. The
no-dwell high bit is ignored in this mode.
With the continuous bidirectional ramp mode activated via an
I/O update or profile change, the internal state machine begins
extracting data from the RAM at the waveform start address and
incrementing the address counter until it reaches the waveform
end address. At this point, the state machine automatically reverses
the direction of the address counter and begins decrementing
through the address range. Whenever one of the terminal
addresses is reached, the state machine reverses the address
counter; the process continues indefinitely.
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