參數(shù)資料
型號(hào)： AD9910BSVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/64頁(yè)
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
Data Sheet
AD9910
Rev. D | Page 33 of 64
RAM CONTROL
RAM Overview
The AD9910 makes use of a 1024 × 32-bit RAM. The RAM has
two fundamental modes of operation: data load/retrieve mode
and playback mode. Data load/retrieve mode is active when the
RAM data is being loaded or read back via the serial I/O port.
Playback mode is active when the RAM enable contents are
routed to one of the internal data destinations.
Depending on the specific playback mode, the user can
partition the RAM with up to eight independent time domain
waveforms. These waveforms drive the DDS signal control
parameters, allowing for frequency, phase, amplitude, or polar
modulated signals.
RAM operations are enabled by setting the RAM enable bit in
Control Function Register 1; an I/O update (or a profile change)
is necessary to enact any change to the state of this bit.
Waveforms are generated using eight RAM profile control
registers that are accessed via the three profile pins. Each profile
contains the following:
10-bit waveform start address word
10-bit waveform end address word
16-bit address step rate control word
3-bit RAM mode control word
No-dwell high bit
Zero-crossing bit
The user must ensure that the end address is greater than the
start address.
Each profile defines the number of samples and the sample rate
for a given waveform. In conjunction with an internal state
machine, the RAM contents are delivered to the appropriate
DDS signal control parameter(s) at the specified rate. Further-
more, the state machine can control the order in which samples
are extracted from RAM (forward/reverse), facilitating efficient
generation of time symmetric waveforms.
Load/Retrieve RAM Operation
It is strongly recommended that RAM enable = 0 when
performing RAM load/retrieve operations. Loading or
retrieving the contents of the RAM requires a three-step
process.
1. Program the RAM Profile 0 through RAM Profile 7 control
registers with the start and end addresses that are to define
the boundaries of each independent waveform.
2. Drive the appropriate logic levels on the profile pins to
select the desired RAM profile.
3. Write to (or read from) the RAM (Address 0x16) the
appropriate number of RAM words as specified by the
selected RAM profile control register (see the Serial
Programming section for details). Figure 41 is a block
diagram showing the functional components used for RAM
data load/retrieve operation.
During RAM load/retrieve operations, the state machine controls
an up/down counter to step through the required RAM loca-
tions. The counter synchronizes with the serial I/O port so that
the serial/parallel conversion of the 32-bit words is correctly
timed with the generation of the appropriate RAM address to
properly execute the desired read or write operation.
RAM
ADDRE
S
DAT
A
Q
SCLK
I/O_RESET
SDIO
CS
PROFILE
WAVEFORM END ADDRESS
WAVEFORM START ADDRESS
ADDRESS CLOCK
PROGRAMMING
REGISTERS
STATE
MACHINE
UP/DOWN
COUNTER
SERIAL
I/O
PORT
2
32
10
U/D
3
06479-
022
Figure 41. RAM Data Load/Retrieve Operation
The RAM profiles are completely independent; it is possible
to define overlapping address ranges. Doing so causes data
that has been written to overlapped address locations to be
overwritten by the most recent write operation.
Multiple waveforms can be loaded into RAM by treating them
as a single waveform, that is, a time-domain concatenation of all
the waveforms. This is done by programming one of the RAM
profiles with a start and end address spanning the entire range
of the concatenated waveforms. Then the single concatenated
waveform is written into RAM via the serial I/O port using the
same RAM profile that was programmed with the start and end
addresses. The RAM profiles must then be programmed with
the proper start and end addresses associated with each
individual waveform.
RAM Playback Operation (Waveform Generation)
When the RAM has been loaded with the desired waveform
data, it can then be used for waveform generation during play
back. RAM playback requires that RAM enable = 1. To play back
RAM data, select the desired waveform using the PROFILE[2:0]
pins. The selected profile directs the internal state machine by
defining the RAM address range occupied by the waveform, the
rate at which samples are to be extracted from the RAM
(playback rate), the mode of operation, and whether to use the
no-dwell feature. Figure 42 is a block diagram showing the
functional components used for RAM playback operation.
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